TM4C1237E6PZ Datasheet, PDF (1175/1306 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1237E6PZ Microcontroller
Bit/Field
6
Name
ISO
Type
RW
5
DMAEN
RW
4
DISNYET / PIDERR
RW
3
DMAMOD
RW
2:0
reserved
RO
Reset
0
Description
Isochronous Transfers
Value Description
0 Enables the receive endpoint for isochronous transfers.
1 Enables the receive endpoint for bulk/interrupt transfers.
0
DMA Request Enable
Value Description
0 Disables the µDMA request for the receive endpoint.
1 Enables the µDMA request for the receive endpoint.
Note:
3 TX and 3 RX endpoints can be connected to the µDMA
module. If this bit is set for a particular endpoint, the DMAARX,
DMABRX, or DMACRX field in the USB DMA Select
(USBDMASEL) register must be programmed
correspondingly.
0
Disable NYET / PID Error
Value Description
0 No effect.
1 For bulk or interrupt transactions: Disables the sending of NYET
handshakes. When this bit is set, all successfully received
packets are acknowledged, including at the point at which the
FIFO becomes full.
For isochronous transactions: Indicates a PID error in the
received packet.
0
DMA Request Mode
Value Description
0 An interrupt is generated after every µDMA packet transfer.
1 An interrupt is generated only after the entire µDMA transfer is
complete.
Note: This bit must not be cleared either before or in the same cycle
as the above DMAEN bit is cleared.
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 12, 2014
Texas Instruments-Production Data
1175