SN75C091A Datasheet, PDF (71/106 Pages) Texas Instruments – SCSI Bus Controller

7.11 timing requirements over recommended operating free-air temperature
and supply voltage ranges
PARAMETER
tw(L) Pulse duration, MRD low
tsu1 Setup time, DACK low before MRD low
th1 Hold time, DACK low after MRD high
td1 Delay time, WAIT high to MRD high
TEST CONDITIONS
See Figure 7–5
MIN MAX UNIT
60
ns
0
ns
0
ns
0
ns
7.12 timing characteristics over recommended operating free-air temperature
and supply voltage ranges
PARAMETER
ten Enable time, MRD low to M(0:7) active
ta Access time, MRD low to M(0:7) valid
tDIS Disable time, MRD high to M(0:7) in high-impedance state
tpd1 Propagation delay, MRD low to DREQ low
tpd2 Propagation delay, DACK high to DREQ high
td2 Delay time, DREQ low to WAIT high
tPHL Propagation delay, high to low, DACK low to WAIT low
TEST
CONDITIONS
CL = 15 PF,
See Figure 7–5
MIN MAX UNIT
5
ns
35 ns
5
25 ns
175 ns
275 ns
55 ns
25 ns
DREQ
DACK
tsu1
tPHL
tpd1
td2
tpd2
th1
WAIT
MRD
td1
tw(L)
M(0:7)
(OUTPUT)
ta
ten
tdis
VALID
NOTE: WAIT timing is shown only for demand-mode transfers that have automatically entered the nondemand mode
due to inadequate FIFO status or approaching end of transfer. The WAIT signal is inactive for nondemand
transfers.
Figure 7–5. DMA Read – Non-Byte-Stack, Nondemand Mode
7–6