LM3S1776 Datasheet, PDF (706/735 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Register Quick Reference
31
30
29
28
27
26
25
15
14
13
12
11
10
9
Cortex-M3 Peripherals
System Control Block (SCB) Registers
Base 0xE000.E000
CPUID, type RO, offset 0xD00, reset 0x411F.C231
IMP
PARTNO
INTCTRL, type R/W, offset 0xD04, reset 0x0000.0000
NMISET
VECPEND
PENDSV UNPENDSV PENDSTSET PENDSTCLR
RETBASE
VTABLE, type R/W, offset 0xD08, reset 0x0000.0000
BASE
OFFSET
APINT, type R/W, offset 0xD0C, reset 0xFA05.0000
ENDIANESS
SYSCTRL, type R/W, offset 0xD10, reset 0x0000.0000
PRIGROUP
24
23
22
21
8
7
6
5
VAR
ISRPRE ISRPEND
OFFSET
VECTKEY
20
19
18
17
16
4
3
2
1
0
VECACT
CON
REV
VECPEND
SYSRESREQ VECTCLRACT VECTRESET
CFGCTRL, type R/W, offset 0xD14, reset 0x0000.0000
SEVONPEND
SLEEPDEEP SLEEPEXIT
SYSPRI1, type R/W, offset 0xD18, reset 0x0000.0000
BUS
SYSPRI2, type R/W, offset 0xD1C, reset 0x0000.0000
SVC
STKALIGN BFHFNMIGN
USAGE
MEM
DIV0 UNALIGNED
MAINPEND BASETHR
SYSPRI3, type R/W, offset 0xD20, reset 0x0000.0000
TICK
SYSHNDCTRL, type R/W, offset 0xD24, reset 0x0000.0000
PENDSV
DEBUG
SVC
BUSP MEMP USAGEP TICK PNDSV
MON SVCA
FAULTSTAT, type R/W1C, offset 0xD28, reset 0x0000.0000
DIV0 UNALIGN
BFARV
BSTKE BUSTKE IMPRE PRECISE IBUS MMARV
HFAULTSTAT, type R/W1C, offset 0xD2C, reset 0x0000.0000
DBG FORCED
MMADDR, type R/W, offset 0xD34, reset -
FAULTADDR, type R/W, offset 0xD38, reset -
Cortex-M3 Peripherals
Memory Protection Unit (MPU) Registers
Base 0xE000.E000
MPUTYPE, type RO, offset 0xD90, reset 0x0000.0800
ADDR
ADDR
ADDR
ADDR
DREGION
USGA
USAGE
BUS
BUSA
MEM
MEMA
NOCP INVPC INVSTAT UNDEF
MSTKE MUSTKE
DERR IERR
VECT
IREGION
SEPARATE
706
November 17, 2011
Texas Instruments-Production Data