LM3S1776 Datasheet, PDF (158/735 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

JTAG Interface
4.3
4.3.1
4.3.1.1
4.3.1.2
Functional Description
A high-level conceptual drawing of the JTAG module is shown in Figure 4-1 on page 157. The JTAG
module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel
update registers. The TAP controller is a simple state machine controlled by the TCK and TMS inputs.
The current state of the TAP controller depends on the sequence of values captured on TMS at the
rising edge of TCK. The TAP controller determines when the serial shift chains capture new data,
shift data from TDI towards TDO, and update the parallel load registers. The current state of the
TAP controller also determines whether the Instruction Register (IR) chain or one of the Data Register
(DR) chains is being accessed.
The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR)
chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load
register determines which DR chain is captured, shifted, or updated during the sequencing of the
TAP controller.
Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not
capture, shift, or update any of the chains. Instructions that are not implemented decode to the
BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see
Table 4-3 on page 164 for a list of implemented instructions).
See “JTAG and Boundary Scan” on page 677 for JTAG timing diagrams.
JTAG Interface Pins
The JTAG interface consists of four standard pins: TCK, TMS, TDI, and TDO. These pins and their
associated reset state are given in Table 4-2 on page 158. Detailed information on each pin follows.
Table 4-2. JTAG Port Pins Reset State
Pin Name
TCK
TMS
TDI
TDO
Data Direction
Input
Input
Input
Output
Internal Pull-Up Internal Pull-Down
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Drive Strength
N/A
N/A
N/A
2-mA driver
Drive Value
N/A
N/A
N/A
High-Z
Test Clock Input (TCK)
The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate
independently of any other system clocks. In addition, it ensures that multiple JTAG TAP controllers
that are daisy-chained together can synchronously communicate serial test data between
components. During normal operation, TCK is driven by a free-running clock with a nominal 50%
duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK
is stopped at 0 or 1, the state of the TAP controller does not change and data in the JTAG Instruction
and Data Registers is not lost.
By default, the internal pull-up resistor on the TCK pin is enabled after reset. This assures that no
clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down
resistors can be turned off to save internal power as long as the TCK pin is constantly being driven
by an external source.
Test Mode Select (TMS)
The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge
of TCK. Depending on the current TAP state and the sampled value of TMS, the next state is entered.
158
November 17, 2011
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