RM57L843 Datasheet, PDF (70/218 Pages) Texas Instruments – Microcontroller Based on the ARM

RM57L843
SPNS215B – FEBRUARY 2014 – REVISED JANUARY 2016
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6.5 ARM Cortex-R5F CPU Information
6.5.1 Summary of ARM Cortex-R5F CPU Features
The features of the ARM Cortex-R5F CPU include:
• An integer unit with integral Embedded ICE-RT logic.
• High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI)
for Level two (L2) master and slave interfaces.
• Floating-Point Coprocessor
• Dynamic branch prediction with a global history buffer, and a 4-entry return stack
• Low interrupt latency.
• Nonmaskable interrupt.
• Harvard Level one (L1) memory system with:
– 32KB of instruction cache and 32KB of data cache implemented. Both Instruction and data cache
have ECC support.
– ARMv7-R architecture Memory Protection Unit (MPU) with 16 regions
• Dual core logic for fault detection in safety-critical applications.
• L2 memory interface:
– Single 64-bit master AXI interface
– 64-bit slave AXI interface to cache memories
– 32-bit AXI_Peri ports to support low latency peripheral ports
• Debug interface to a CoreSight Debug Access Port (DAP).
• Performance Monitoring Unit (PMU).
• Vectored Interrupt Controller (VIC) port.
• AXI accelerator coherency port (ACP) supporting IO coherency with write-through cacheable regions
• Ability to generate ECC on L2 data buses and parity of all control channels
• Both CPU cores in lock-step
• 8 hardware breakpoints
• 8 watchpoints
6.5.2 Dual Core Implementation
The device has two Cortex-R5F cores, where the output signals of both CPUs are compared in the CCM-
R5F unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed by two
clock cycles as shown in Figure 6-2.
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System Information and Electrical Specifications
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