RM57L843 Datasheet, PDF (161/218 Pages) Texas Instruments – Microcontroller Based on the ARM

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RM57L843
SPNS215B – FEBRUARY 2014 – REVISED JANUARY 2016
7.3 Enhanced Quadrature Encoder (eQEP)
Figure 7-6 shows the eQEP module interconnections on the device.
EPWM1/../7
Connection
Selection
Mux
VIM
VIM
VBus32
EQEP1ENCLK
VCLK3
SYS_nRST
EQEP1INTn
EQEP1
Module
EQEP1ERR
EQEP1A
see Note A EQEP1B
EQEP1I
EQEP1IO
EQEP1IOE
EQEP1S
EQEP1SO
EQEP1SOE
VBus32
EQEP2ENCLK
VCLK3
SYS_nRST
EQEP2INTn
EQEP2ERR
EQEP2
Module
EQEP2A
see Note A EQEP2B
EQEP2I
EQEP2IO
EQEP2IOE
EQEP2S
EQEP2SO
EQEP2SOE
IO
Mux
A. For more detail on the eQEPx input synchronization selection, see Figure 7-7.
Figure 7-6. eQEP Module Interconnections
Figure 7-7 shows the detailed input synchronization selection (asynchronous, double-synchronous, or
double synchronous + filter width) for eQEPx.
eQEPx
(x = 1 or 2)
double
sync
6 VCLK3
Cycles Filter
EQEPxA or EQEPxB
(x = 1 or 2)
Figure 7-7. eQEPx Input Synchronization Selection Detail
7.3.1 Clock Enable Control for eQEPx Modules
Each of the EQEPx modules has a clock enable (EQEPxENCLK) which is controlled by its respective
Peripheral Power Down bit in the PSPWRDWNCLRx register of the PCR2 module. To properly reset the
peripherals, the peripherals must be released from reset by setting the PENA bit of the CLKCNTL register
in the system module. In additional, the peripherals must be released from their power down state by
clearing their respective bit in the PSPWRDWNCLRx register. By default after reset, the peripherals are in
power down state.
ePWM MODULE INSTANCE
eQEP1
eQEP2
Table 7-11. eQEPx Clock Enable Control
CONTROL REGISTER TO ENABLE
CLOCK
PSPWRDWNCLR3[5]
PSPWRDWNCLR3[6]
DEFAULT VALUE
1
1
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Peripheral Information and Electrical Specifications 161
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