TMS470R1A256_09 Datasheet, PDF (7/48 Pages) Texas Instruments – 16/32-Bit RISC Flash Microcontroller

www.ti.com
TMS470R1A256
16/32-Bit RISC Flash Microcontroller
SPNS100B – NOVEMBER 2004 – REVISED AUGUST 2006
Table 2. Terminal Functions
TERMINAL
NAME
PIN
NUMBER
HET[0]
91
HET[1]
-
HET[2]
97
HET[3]
-
HET[4]
98
HET[5]
-
HET[6]
99
HET[7]
100
HET[8]
55
HET[9]
-
HET[10]
20
HET[11]
19
HET[12]
18
HET[13]
17
HET[14]
-
HET[15]
-
HET[16]
-
HET[17]
-
HET[18]
49
HET[19]
48
HET[20]
47
HET[21]
46
HET[22]
-
HET[24]
35
HET[28]
-
HET[29]
-
HET[30]
-
HET[31]
34
CANSRX
59
CANSTX
60
C2SILPN
36
C2SIRX
38
C2SITX
37
TYPE ^{(1) (2)}
INTERNAL
PULLUP/
PULLDOWN ⁽³⁾
HIGH-END TIMER (HET)
DESCRIPTION
3.3-V I/O
The A256 devices have both the logic and registers for a full 32-I/O
HET implemented, even though not all 32 pins are available
externally
Timer input capture or output compare. The HET[31:0] applicable
pins can be programmed as general-purpose input/output (GIO)
pins.
HET[21:18, 13:10, 8:6, 4, 2, 0] are high-resolution pins and HET[31,
24] are standard-resolution pins for A256.
The high-resolution (HR) SHARE feature allows even-numbered HR
pins to share the next higher odd-numbered HR pin structures. This
HR sharing is independent of whether or not the odd pin is available
IPD
externally. If an odd pin is available externally and shared, then the
odd pin can only be used as a general-purpose I/O. For more
information on HR SHARE, see the TMS470R1x High-End Timer
(HET) Reference Guide (literature number SPNU199).
The HET[19] or HET[18] pins can also be used as a user-selectable
event source to event trigger the MibADC event group or group1 if
the associated register source bits are properly configured and
defined. For the internal device connections, see the MibADC
section of this data sheet. For more detailed functional information
on the MibADC, see the TMS470R1x Multi-Buffered
Analog-to-Digital Converter (MibADC) Reference Guide (literature
number SPNU206).
3.3-V I/O
3.3-V I/O
3.3-V I/O
3.3-V I/O
3.3-V I/O
STANDARD CAN CONTROLLER (SCC)
SCC receive pin or GIO pin
IPU
SCC transmit pin or GIO pin
CLASS II SERIAL INTERFACE (C2SIb)
IPD
C2SIb module loopback enable pin or GIO pin
C2SIb module receive data input pin or GIO pin
IPD
C2SIb module transmit data output pin or GIO pin
(1) I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect
(2) All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
(3) IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST
state.)
Submit Documentation Feedback
7