TMS470R1A256_09 Datasheet, PDF (34/48 Pages) Texas Instruments – 16/32-Bit RISC Flash Microcontroller

TMS470R1A256
16/32-Bit RISC Flash Microcontroller
SPNS100B – NOVEMBER 2004 – REVISED AUGUST 2006
SPIn SLAVE MODE TIMING PARAMETERS
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SPIn Slave Mode External Timing Parameters
(CLOCK PHASE = 0, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output)^(1)(2)(3)(4) (see Figure 14)
NO.
1
2 ⁽⁶⁾
t_c(SPC)S
t_w(SPCH)S
t_w(SPCL)S
3 ⁽⁶⁾
t_w(SPCL)S
t_w(SPCH)S
4 ⁽⁶⁾
t_{d(SPCH-SOMI)S}
t_{d(SPCL-SOMI)S}
5 ⁽⁶⁾
t_{v(SPCH-SOMI)S}
t_{v(SPCL-SOMI)S}
6 ⁽⁶⁾
t_{su(SIMO-SPCL)S}
t_{su(SIMO-SPCH)S}
7 ⁽⁶⁾
t_{v(SPCL-SIMO)S}
t_{v(SPCH-SIMO)S}
Cycle time, SPInCLK⁽⁵⁾
Pulse duration, SPInCLK high
(clock polarity = 0)
Pulse duration, SPInCLK low
(clock polarity = 1)
Pulse duration, SPInCLK low
(clock polarity = 0)
Pulse duration, SPInCLK high
(clock polarity = 1)
Delay time, SPInCLK high to
SPInSOMI valid (clock polarity = 0)
Delay time, SPInCLK low to
SPInSOMI valid (clock polarity = 1)
Valid time, SPInSOMI data valid after
SPInCLK high (clock polarity = 0)
Valid time, SPInSOMI data valid after
SPInCLK low (clock polarity = 1)
Setup time, SPInSIMO before
SPInCLK low (clock polarity = 0)
Setup time, SPInSIMO before
SPInCLK high (clock polarity = 1)
Valid time, SPInSIMO data valid after
SPInCLK low (clock polarity = 0)
Valid time, SPInSIMO data valid after
SPInCLK high (clock polarity = 1)
MIN
100
0.5t_c(SPC)S - 0.25t_c(ICLK)
0.5t_c(SPC)S - 0.25t_c(ICLK)
0.5t_c(SPC)S - 0.25t_c(ICLK)
0.5t_c(SPC)S - 0.25t_c(ICLK)
t_c(SPC)S - 6 - t_r
t_c(SPC)S - 6 - t_f
6
6
6
6
MAX
256t_c(ICLK)
0.5t_c(SPC)S + 0.25t_c(ICLK)
0.5t_c(SPC)S + 0.25t_c(ICLK)
0.5t_c(SPC)S + 0.25t_c(ICLK)
0.5t_c(SPC)S + 0.25t_c(ICLK)
6 + t_r
6 + t_f
UNIT
ns
ns
ns
ns
ns
ns
ns
(1) The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2[1]) is cleared.
(2) If the SPI is in slave mode, the following must be true: t_c(SPC)S≥ (PS + 1) t_c(ICLK), where PS = prescale value set in SPInCTL1[12:5].
(3) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
(4) t_c(ICLK) = interface clock cycle time = 1 /f_(ICLK)
(5) When the SPIn is in slave mode, the following must be true:
For PS values from 1 to 255: t_c(SPC)S ≥ (PS +1)t_c(ICLK)≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: t_c(SPC)S = 2t_c(ICLK) ≥ 100 ns.
(6) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2[1).
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