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TAS2560 Datasheet, PDF (7/80 Pages) Texas Instruments – 5.6-W Class-D Mono Audio Amplifier with IV Sense
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TAS2560
SLASE86B – JUNE 2016 – REVISED AUGUST 2016
Electrical Characteristics (continued)
VBAT = 3.6 V, VDD = IOVDD = 1.8 V, RESETZ = IOVDD, Gain = 16.4 dB, ERC = 14 ns, Boost Inductor = 2.2 µH, RL = 8 Ω +
33 µH, 1-kHz input frequency, 48-kHz sample rate for digital input, Class-H Boost Enabled, TA= 25°C, ILIM = 3 A (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
CURRENT SENSE
Peak current which will give full scale
digital output 8-Ω load
1.25
Current sense full scale
Peak current which will give full scale
digital output 8-Ω load PDM
Peak current which will give full scale
digital output 6-Ω load
4.022
1.5
APEAK
Peak current which will give full scale
digital output 4-Ω load
1.75
Current sense accuracy
Current sense gain drift over
temperature
IOUT = 354 mARMS (1 W)
–40°C to 85°C
1.7%
4%
Current sense gain linearity
From 15 mW to 3.5 W for fin=1 kHz
1.5%
THD+N Distortion + Noise
SNR
POUT = 3 W (Load = 8 Ω + 33 µH)
POUT = 3 W (Load = 4 Ω + 33 µH)
20 Hz to 20 kHz, A-wt
0.196%
0.132%
–68
db
VOLTAGE SENSE
Voltage sense full scale
Peak voltage which will give full scale
digital output(1)
Peak voltage which will give full scale
digital output in PDM
9.353
16.65
VPEAK
Voltage sense accuracy
Voltage sense gain drift over
temperature
VOUT = 2.83 Vrms (1 W)
–40°C to 85°C
1%
1.2%
Voltage sense gain linearity
From 15 mW to 3.5 W for fin = 1 kHz
1%
INTERFACE
Voltage and current sense data rate
Voltage and current sense ADC OSR
TDM/I2S
TDM/I2S
48
kHz
64
OSR
FMCLK MCLK frequency
POWER CONSUMPTION
0.512
49.15 MHz
Power consumption with digital input
and IV-sense disabled. Idle channel
condition
From VBAT, no signal
From VDD, no signal
3.2
mA
9.5
mA
Power consumption with digital input From VBAT, no signal
and IV-sense enabled.
From VDD, no signal
3.2
mA
10.6
mA
Power consumption in hardware
shutdown
From VBAT, RESETZ = 0
From VDD, RESETZ = 0
0.1
µA
1.2
µA
Power consumption in software
shutdown. See Low Power Sleep
From VBAT
From VDD
0.1
µA
9.8
µA
DIGITAL INPUT / OUTPUT
VIH
High-level digital input voltage
VIL
Low-level digital input voltage
All digital pins except SDA and SCL,
IOVDD = 1.8-V operation
0.65 ×
IOVDD
V
0.35 ×
IOVDD
V
VIH
High-level digital input voltage
VIL
Low-level digital input voltage
All digital pins except SDA and SCL,
IOVDD = 3.3-V operation
2
V
0.45
V
(1) Voltage Sense Fullscale = 1.176 Vrms × 10(DAC_GAIN/20)
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