TAS2560 Datasheet, PDF (58/80 Pages) Texas Instruments – 5.6-W Class-D Mono Audio Amplifier with IV Sense

TAS2560
SLASE86B – JUNE 2016 – REVISED AUGUST 2016
Table 78. ASI BDIV Configuration Field Descriptions (continued)
Bit Field
6-0 ASI_BDIV_RATIO[6:0]
Type
RW
Reset
1h
Description
The ASI_BDIV ration is
0 = 128
1-31 = Reserved
32 = 32
33 = 33
...
126 = 126
127 = 127
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9.7.21 ASI_WDIV (book=0x00 page=0x00 address=0x1B) [reset=40h]
ASI WDIV Configuration
Figure 76. ASI_WDIV Register Address: 0x1B
7
6
5
4
3
2
1
0
ASI_WDIV_P
ASI_WDIV_RATIO[6:0]
RW-0h
RW-40h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 79. ASI WDIV Configuration Field Descriptions
Bit Field
7
ASI_WDIV_P
6-0 ASI_WDIV_RATIO[6:0]
Type
RW
Reset
0h
RW
40h
Description
ASI WDIV divider is
0 = Powered down
1 = Powered up
The ASI_WDIV ration is
0 = 128
1-31 = Reserved
32 = 32
33 = 33
...
126 = 126
127 = 127
9.7.22 PDM_CFG (book=0x00 page=0x00 address=0x1C) [reset=0h]
PDM Configuration
Figure 77. PDM_CFG Register Address: 0x1C
7
6
5
4
3
Reserved
Reserved
RW-0h
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
2
PDM_CLK_E
RW-0h
1
PDM_CI_M
RW-0h
0
PDM_CIO_M
RW-0h
Bit Field
7-5 Reserved
4-3 Reserved
2
PDM_CLK_E
1
PDM_CI_M
0
PDM_CIO_M
Table 80. PDM Configuration Field Descriptions
Type
RW
RW
RW
Reset
0h
0h
0h
RW
0h
RW
0h
Description
Reserved
Reserved
Data is latch on the following edge of the PDM clock
0 = Rising
1 = Falling
PDM_IN_CLK direction is
0 = input
1 = output
PDM_OUT_CLK direction is
0 = input
1 = output
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