MSP430FR573X Datasheet, PDF (7/109 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

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Functional Block Diagram –
MSP430FR5721IDA, MSP430FR5725IDA, MSP430FR5729IDA,
MSP430FR5731IDA, MSP430FR5735IDA, MSP430FR5739IDA
PJ.4/XIN PJ.5/XOUT
DVCC DVSS VCORE AVCC AVSS
MSP430FR573x
MSP430FR572x
SLAS639D – JULY 2011 – REVISED AUGUST 2012
PA
P1.x P2.x
PB
P3.x
Clock
System
ACLK
SMCLK
16 KB
(’5739, ’5729)
8 KB
(’5735, ‘5725)
4 KB
(’5731, ‘5721)
MCLK
FRAM
Memory
Protection
Unit
CPUXV2
and
Working
Registers
MAB
MDB
1 KB
RAM
Boot
ROM
Power
Management
SVS
SYS
Watchdog
REF
I/O Ports
P1/P2
2×8 I/Os
Interrupt
& Wakeup
PA
1×16 I/Os
I/O Ports
P3
1×8 I/Os
Interrupt
& Wakeup
PB
1×8 I/Os
DMA
3 Channel
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
EEM
(S: 3+1)
JTAG/
SBW
Interface
MPY32
TA0
TB0
TA1
TB1
TB2
(2) Timer_A (3) Timer_B
3 CC
3 CC
Registers Registers
RTC_B
CRC
eUSCI_A0:
UART,
IrDA, SPI
eUSCI_B0:
SPI, I2C
eUSCI_A1:
UART,
IrDA, SPI
ADC10_B
10 Bit
200KSPS
Comp_D
16 channels
16 channels
(12 ext/2 int)
Functional Block Diagram –
MSP430FR5723IDA, MSP430FR5727IDA,
MSP430FR5733IDA, MSP430FR5737IDA
PJ.4/XIN PJ.5/XOUT
DVCC DVSS VCORE AVCC AVSS
Clock
System
ACLK
SMCLK
16 KB
(’5737, ’5727)
8 KB
(’5733, ‘5723)
MCLK
FRAM
Memory
Protection
Unit
CPUXV2
and
Working
Registers
MAB
MDB
1 KB
RAM
Boot
ROM
Power
Management
SVS
SYS
Watchdog
PA
P1.x P2.x
PB
P3.x
I/O Ports
P1/P2
2×8 I/Os
Interrupt
& Wakeup
PA
1×16 I/Os
I/O Ports
P3
1×8 I/Os
Interrupt
& Wakeup
PB
1×8 I/Os
DMA
3 Channel
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
EEM
(S: 3+1)
JTAG/
SBW
Interface
MPY32
TA0
TB0
TA1
TB1
TB2
(2) Timer_A (3) Timer_B
3 CC
3 CC
Registers Registers
RTC_B
CRC
eUSCI_A0:
UART,
IrDA, SPI
eUSCI_B0:
SPI, I2C
eUSCI_A1:
UART,
IrDA, SPI
REF
Comp_D
16 channels
Copyright © 2011–2012, Texas Instruments Incorporated
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