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| HD3SS3412_16 Datasheet, PDF (7/27 Pages) Texas Instruments – 4-Channel High-Performance Differential Switch | |||
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www.ti.com
HD3SS3412
SLAS828E â FEBRUARY 2012 â REVISED JANUARY 2016
7.2 ESD Ratings
V(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-
C101 (2)
VALUE
±4000
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
UNIT
V
7.3 Recommended Operating Conditions
Typical values for all parameters are at VDD = 3.3 V and TA = 25°C. (Temperature limits are specified by design)
MIN NOM MAX
VDD
VIH
VIL
VI/O_Diff
VI/O_CM
TA
Supply voltage
Input high voltage (SEL pin)
Input low voltage (SEL pin)
Differential voltage (differential pins)
Common voltage (differential pins)
Operating free-air temperature
Switch I/O diff voltage
Switch I/O common-mode voltage
Ambient temperature
3.0 3.3
3.6
2.0
VDD
â0.1
0.8
0
1.8
0
2.0
0
70
UNIT
V
V
V
VPP
V
oC
7.4 Thermal Information
THERMAL METRIC(1)
HD3SS3412
RUA (WQFN)
UNIT
42 PINS
RθJA
RθJC(top)
RθJB
ÏJT
ÏJB
RθJC(bot)
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
53.8
°C/W
38.2
°C/W
21.9
°C/W
27.4
°C/W
5.6
°C/W
27.3
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DEVICE PARAMETERS
IIH
IIL
ILK
IDD
CON
COFF
RON
ÎRON
Input High Voltage (SEL)
Input Low Voltage (SEL)
Leakage Current (Differential
I/O pins)
Supply Current
Outputs ON Capacitance
Outputs OFF Capacitance
Output ON resistance
ON-resistance match between
channels
VDD = 3.6 V; VIN = VDD
VDD = 3.6 V; VIN = GND
VDD = 3.6 V; VIN = 0 V; VOUT = 2 V
(ILK On OPEN outputs) [Ports B and C]
VDD = 3.6 V, VIN = 2 V; VOUT = 0 V
(ILK On OPEN outputs) [Port A]
VDD = 3.6 V; SEL = VDD/GND; Outputs Floating
VIN = 0 V; Outputs Open; Switch ON
VIN = 0 V; Outputs Open, Switch OFF
VDD = 3.3 V; VCM = 0.5 V to 1.5 V ; IO = â8 mA
VDD = 3.3 V ; â0.35 V ⤠VIN ⤠1.2 V; IO = â8 mA
ON-resistance match between
pairs of the same channel
VDD = 3.3 V; â0.35 V ⤠VIN ⤠1.2 V; IO = â8 mA
RFLAT_ON
tPD
ON-resistance flatness
(RON(MAX) â RON(MAIN)
Switch propagation delay
VDD = 3.3 V; â0.35 V ⤠VIN ⤠1.2 V
Rsc and RLOAD = 50 Ω
MIN TYP MAX UNIT
95
µA
1
µA
130
µA
4
4.7
6 mA
1.5
pF
1
pF
5
8
Ω
2
Ω
0.7
Ω
1.15
Ω
85
ps
Copyright © 2012â2016, Texas Instruments Incorporated
Product Folder Links: HD3SS3412
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