HD3SS3412_16 Datasheet, PDF (17/27 Pages) Texas Instruments – 4-Channel High-Performance Differential Switch

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HD3SS3412
SLAS828E – FEBRUARY 2012 – REVISED JANUARY 2016
Typical Application (continued)
10.2.1 Design Requirements
Table 3 lists the design parameters of this example.
Table 3. Design Parameters
DESIGN PARAMETERS
Input voltage range
Decoupling capacitors
AC capacitors
EXAMPLE VALUE
3.3 V
0.1 µF
75 nF – 200 nF (100 nF shown) USBAA TX p and
n lines require AC capacitors. Alternate mode
signals may or may not require AC capacitors
10.2.2 Detailed Design Procedure
• Connect VDD and GND pins to the power and ground planes of the printed circuit board, with 0.1-uF bypass
capacitor
• Use +3.3-V TTL/CMOS logic level at SEL
• Use controlled-impedance transmission media for all the differential signals
• Ensure the received complimentary signals are with a differential amplitude of <1800 mVpp and a common-
mode voltage of <2 V
10.2.3 Application Curves
Figure 15. 10-gbps Source Eye Diagram at a: V_ID = 800
Mvpp; 2⁷–1 Prbs; V_CM= 0 V
Figure 16. 10-gbps Output Eye Diagram at a: V_ID = 800
Mvpp; 2⁷–1 Prbs; V_CM= 0v; V_DD= 3.3 V; Sel= 0 V
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