DS89C387_16 Datasheet, PDF (7/15 Pages) Texas Instruments – Twelve Channel CMOS Differential Line Driver

DS89C387
www.ti.com
SNLS101E – MAY 1995 – REVISED APRIL 2013
In Figure 4, VX, where X is a number, is the waveform voltage level at which the propagation delay
measurement either starts or stops. Furthermore, V1 and V2 are normally identical. The same is true for V3 and
V4. However, as mentioned before, these levels are not standardized and may vary, even with similar devices
from other companies. Also note, NC (no connection) in Figure 3 means the pin is not used in propagation delay
measurement for the corresponding circuit.
The single-ended skew provides information about the pulse width distortion of the output waveform. The lower
the skew, the less the output waveform will be distorted. For best case, skew would be zero, and the output duty
cycle would be 50%, assuming the input has a 50% duty cycle.
Figure 12. (Circuit 3) – Circuit for Measuring Differential Propagation Delays
(See Figure 13)
Figure 13. Waveforms for Circuit 3 – Propagation Delay Waveforms
for Circuit 3
(See Figure 12)
For differential propagation delays, V1 should equal V2. Furthermore, the crossing point of DO and DO*
corresponds to zero volts on the differential waveform (see bottom waveform in Figure 13). This is true whether
V3 equals V4 or not. However, if V3 and V4 are specified voltages, then V3 and V4 are less likely to be equal to
the crossing point voltage. Thus, the differential propagation delays will not be measured to zero volts on the
differential waveform.
The differential skew also provides information about the pulse width distortion of the differential output waveform
relative to the input waveform. The higher the skew, the greater the distortion of the differential output waveform.
Assuming the input has a 50% duty cycle, the differential output will have a 50% duty cycle if skew equals zero
and less than a 50% duty cycle if skew is greater than zero.
Figure 14. (Circuit 4) – Circuit for Measuring Complementary Skew
(See Figure 15)
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