CD74HC595_14 Datasheet, PDF (7/22 Pages) Texas Instruments – 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS

CD74HC595
8ĆBIT SHIFT REGISTERS
WITH 3ĆSTATE OUTPUT REGISTERS
SCHS353 − JANUARY 2004
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
TA = 25°C
TA = -55°C TO TA = -40°C TO
125°C
85°C
MIN MAX MIN MAX MIN MAX
UNIT
2V
6
4.2
5
fclock Clock frequency
4.5 V
6V
31
21
25 MHz
36
25
29
2V
80
120
100
SRCLK or RCLK high or low
4.5 V
16
24
20
tw
Pulse duration
6V
14
20
17
ns
2V
80
120
100
SRCLR low
4.5 V
16
24
20
6V
14
20
17
2V
100
150
125
SER before SRCLK↑
4.5 V
20
30
25
6V
17
25
21
2V
75
113
94
SRCLK↑ before RCLK↑^†
4.5 V
15
23
19
tsu
Setup time
6V
13
19
16
ns
2V
50
75
65
SRCLR low before RCLK↑
4.5 V
10
15
13
6V
9
13
11
2V
50
75
60
SRCLR high (inactive) before SRCLK↑ 4.5 V
10
15
12
6V
9
13
11
2V
0
0
0
th
Hold time, SER after SRCLK↑
4.5 V
0
0
0
ns
6V
0
0
0
† _{This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift}
register is one clock pulse ahead of the storage register.
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