CD74HC595_14 Datasheet, PDF (10/22 Pages) Texas Instruments – 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS

CD74HC595
8ĆBIT SHIFT REGISTERS
WITH 3ĆSTATE OUTPUT REGISTERS
SCHS353 − JANUARY 2004
PARAMETER MEASUREMENT INFORMATION
Test
From Output ^{Point RL}
Under Test
CL
(see Note A)
VCC
S1
S2
LOAD CIRCUIT
PARAMETER RL
tPZH
ten
1 kΩ
tPZL
tdis
tPHZ _{1 kΩ}
tPLZ
tpd or tt
−−
CL
50 pF
or
150 pF
S1
Open
Closed
Open
50 pF
Closed
50 pF
or
150 pF
Open
S2
Closed
Open
Closed
Open
Open
High-Level
Pulse
Low-Level
Pulse
50%
tw
50%
50%
50%
VOLTAGE WAVEFORMS
PULSE DURATIONS
VCC
0V
VCC
0V
Reference
Input
Data
Input
50%
10%
tsu
90%
tr
50%
th
90%
VCC
0V
VCC
50%
10% _{0 V}
tf
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
Input
In-Phase
Output
Out-of-
Phase
Output
50%
tPLH
50%
10%
tPHL
90%
90%
tr
50%
10%
tf
50%
tPHL
90%
tPLH
50%
10%
VCC
0V
VOH
50%
10% _VOL
tf
90% ^VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
Output
Control
(Low-Level
Enabling)
tPZL
Output
Waveform 1
(See Note B)
tPZH
Output
Waveform 2
(See Note B)
50%
50%
≈VCC
50%
50%
VCC
tPLZ
0V
≈VCC
10% _VOL
tPHZ
90% ^VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. For clock inputs, fmax is measured when the input duty cycle is 50%.
E. The outputs are measured one at a time, with one input transition per measurement.
F. tPLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
H. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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