ADS6425_14 Datasheet, PDF (7/60 Pages) Texas Instruments – QUAD CHANNEL, 12-BIT, 125-MSPS ADC WITH SERIAL LVDS INTERFACE

ADS6425
www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009
TIMING SPECIFICATIONS⁽¹⁾
Typical values are at 25°C, min and max values are across the full temperature range T_MIN = –40°C to T_MAX = 85°C, AVDD =
LVDD = 3.3 V, sampling frequency = 125 MSPS, sine wave input clock, 1.5 V_PP clock amplitude, C_L = 5 pF ⁽²⁾, I_O = 3.5 mA,
R_L = 100 Ω ⁽³⁾, no internal termination, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
t_J
Aperture jitter
Uncertainty in the sampling instant
Interface: 2-wire, DDR bit clock, 12x serialization ⁽⁴⁾
250
fs rms
t_su
Data setup time^{(5) (6)}
Measured from zero crossing of data transitions to
zero crossing of bit clock
0.4
0.6
ns
t_h
Data hold time^{(5) (6)}
Measured from zero crossing of bit clock to zero
crossing of data transitions
0.5
0.7
ns
t_su
Frame setup time
Measured from zero-cross of frame clock rising
edge to zero-cross of bit clock rising edge
0.4
0.6
ns
t_h
Frame hold time
Measured from zero-cross of bit clock falling edge
to zero-cross of frame clock falling edge
0.5
0.7
ns
t_{pd_clk}
Clock propagation delay⁽⁴⁾
Bit clock cycle-cycle jitter ⁽⁶⁾
Frame clock cycle-cycle jitter ⁽⁶⁾
Input clock rising edge cross-over to frame clock
rising edge cross-over
3.6
4.4
350
75
5.2 ns
ps pp
ps pp
Below specifications apply for 5 MSPS ≤ Fs ≤125 MSPS and all interface options.
t_A
Aperture delay
Delay from rising edge of input clock to the actual
sampling instant
1
2
3 ns
Aperture delay variation,
channel-channel
Within the same device
-250
250 ps
ADC Latency ⁽⁷⁾
Time for a sample to propagate to the ADC output
Figure 1
12
Clock
cycles
Time to valid data after coming out of global power
down
100 µs
Wake up time
Time to valid data after input clock is re-started
100 µs
Time to valid data after coming out of channel
standby
200
clock
cycles
t_RISE
Data rise time
Data rise time measured from –100 mV to +100
mV
50
100
200 ps
t_FALL
t_RISE
t_FALL
Data fall time
Bit clock and frame clock rise time
Bit clock and frame clock fall time
LVDS Bit clock duty cycle
Data fall time measured from +100 mV to –100 mV
Rise time measured from –100mV to +100mV
Fall time measured from +100mV to –100mV
50
100
200 ps
50
100
200 ps
50
100
200 ps
45% 50% 55%
LVDS Frame clock duty cycle
47% 50% 53%
(1) Timing parameters are ensured by design and characterization and not tested in production.
(2) C_L is the external single-ended load capacitance between each output pin and ground.
(3) I_o refers to the LVDS buffer current setting; R_L is the external differential load resistance between the LVDS output pair.
(4) Refer to Output Timings in application section for timings at lower sampling frequencies and other interface options.
(5) Timing parameters are measured at the end of a 2 inch pcb trace (100-Ω characteristic impedance) terminated by R_Land C_L.
(6) Setup and hold time specifications take into account the effect of jitter on the output data and clock.
(7) Note that the total latency = ADC latency + internal serializer latency. The serializer latency depends on the interface option selected as
shown in Table 25
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS6425
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