ADS6425_14 Datasheet, PDF (40/60 Pages) Texas Instruments – QUAD CHANNEL, 12-BIT, 125-MSPS ADC WITH SERIAL LVDS INTERFACE

ADS6425
SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com
Input Clock,
CLK
Freq = Fs
Frame Clock,
FCLK
Freq = 1 ´ Fs
Bit Clock – SDR,
DCLK
Freq = 6 ´ Fs
Bit Clock – DDR,
DCLK
Freq = 3 ´ Fs
Output Data D5 D4 D3 D2 D1 D0 D5 D4 D3 D2 D1 D0
DA0, DB0, DC0, DD0 ^{(D0) (D1) (D2) (D3) (D4) (D5) (D0) (D1) (D2) (D3) (D4) (D5)}
Output Data
DA1, DB1, DC1, DD1
D11 D10 D9 D8 D7 D6 D11 D10 D9 D8 D7 D6
(D6) (D7) (D8) (D9) (D10) (D11) (D6) (D7) (D8) (D9) (D10) (D11)
Data Rate = 6 ´ Fs
Output Data D10 D8 D6 D4 D2 D0 D10 D8 D6 D4 D2 D0
DA0, DB0, DC0, DD0 ^{(D0) (D2) (D4) (D6) (D8) (D10) (D0) (D2) (D4) (D6) (D8) (D10)}
Output Data D11 D9 D7 D5 D3 D1 D11 D9 D7 D5 D3 D1
DA1, DB1, DC1, DD1 ^{(D1) (D3) (D5) (D7) (D9) (D11) (D1) (D3) (D5) (D7) (D9) (D11)}
Output Data D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DA0, DB0, DC0, DD0 ^{(D0) (D1) (D2) (D3) (D4) (D5) (D6) (D7) (D8) (D9) (D10) (D11)}
Output Data D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DA1, DB1, DC1, DD1 ^{(D0) (D1) (D2) (D3) (D4) (D5) (D6) (D7) (D8) (D9) (D10) (D11)}
Data Bit in MSB First Mode
White Cells – Sample N
D5
(D0)
Data Bit in LSB First Mode
Grey Cells – Sample N + 1
T0226-01
A. In the byte-wise and bit-wise modes, the frame clock frequency is 1 x Fs. In the word-wise mode, the frame clock
frequency is 0.5 x Fs.
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