ADS58C28_16 Datasheet, PDF (7/68 Pages) Texas Instruments – Dual Channel IF Receiver with SNRBoost 3G

ADS58C28
www.ti.com
SBAS509B – JUNE 2010 – REVISED OCTOBER 2010
DIGITAL CHARACTERISTICS
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at valid logic
level 0 or 1. AVDD = 1.8V and DRVDD = 1.8V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DIGITAL INPUTS—RESET, SCLK, SDATA, SEN, CTRL1, CTRL2, and CTRL3
High-level input voltage
Low-level input voltage
RESET, SCLK, SDATA and SEN support
1.8V and 3.3V CMOS logic levels.
High-level input
current
SDATA, SCLK⁽¹⁾
SEN ⁽²⁾
V_HIGH = 1.8V
V_HIGH = 1.8V
Low-level input
current
SDATA, SCLK
SEN
V_LOW = 0V
V_LOW = 0V
DIGITAL OUTPUTS—CMOS INTERFACE (CHx_Dn, SDOUT)
1.3
10
0
0
–10
V
0.4 V
µA
µA
µA
µA
High-level output voltage
DRVDD – 0.1 DRVDD
V
Low-level output voltage
0
0.1 V
DIGITAL OUTPUTS—LVDS INTERFACE (CHxP/M, CLKOUTP/M)
V_ODH, High-level output voltage⁽³⁾
V_ODL, Low-level output voltage⁽³⁾
V_ODH, High-level output voltage⁽³⁾
V_ODL, Low-level output voltage⁽³⁾
Standard swing LVDS
Standard swing LVDS
Low swing LVDS⁽⁴⁾
Low swing LVDS⁽⁴⁾
V_OCM, Output common-mode voltage
270
–430
0.9
350
–350
200
–200
1.05
430 mV
–270 mV
mV
mV
1.25 V
(1) SDATA and SCLK have an internal 150kΩ pull-down resistor.
(2) SEN has an internal 150kΩ pull-up resistor to AVDD.
(3) With external 100Ω termination.
(4) See the LVDS Output Data and Clock Buffers section.
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): ADS58C28
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