ADS5273_14 Datasheet, PDF (7/33 Pages) Texas Instruments – 8-Channel, 12-Bit, 70MSPS Analog-to-Digital Converter

ADS5273
www.ti.com .............................................................................................................................................. SBAS305D – JANUARY 2004 – REVISED JANUARY 2009
LVDS DIGITAL DATA AND CLOCK OUTPUTS
Test conditions at I_O = 3.5mA, R_LOAD = 100Ω, C_LOAD = 6pF, and 50% duty cycle. I_O refers to the current setting for the LVDS buffer. R_LOAD is
the differential load resistance between the differential LVDS pair. C_LOAD is the effective single-ended load capacitance between each of the
LVDS pins and ground. C_LOAD includes the receiver input parasitics as well as the routing parasitics. Measurements are done with a 1-inch
transmission line of 100Ω characteristic impedance between the device and the load. All LVDS specifications are characterized, but not
parametrically tested at production. LCLKOUT refers to (LCLK_P – LCLK_N); ADCLKOUT refers to (ADCLK_P – ADCLK_N); DATA OUT refers to
(OUT_P – OUT_N); and ADCLK refers to the input sampling clock.
PARAMETER
DC SPECIFICATIONS⁽¹⁾
CONDITIONS
MIN TYP MAX UNITS
V_OH Output Voltage High, OUT_P or OUT_N
V_OL Output Voltage Low, OUT_P or OUT_N
|V_OD| Output Differential Voltage
V_OS Output Offset Voltage⁽²⁾
R_O Output Impedance, Differential
R_O Output Impedance, Differential
C_O Output Capacitance⁽³⁾
|ΔV_OD| Change in |V_OD| Between 0 and 1
ΔV_OS Change Between 0 and 1
ISOUT Output Short-Circuit Current
R_LOAD = 100Ω ± 1%; See LVDS Timing Diagram, Page 8 1265 1365 1465
mV
R_LOAD = 100Ω ± 1%
940 1040 1140 mV
R_LOAD = 100Ω ± 1%
275
325
375
mV
R_LOAD = 100Ω ± 1%; See LVDS Timing Diagram, Page 8 1.1
1.2
1.3
V
Normal Operation
13
kΩ
Power-Down
20
kΩ
4
pF
R_LOAD = 100Ω ± 1%
R_LOAD = 100Ω ± 1%
Drivers Shorted to Ground
10
mV
25
mV
40
mA
ISOUT_NP Output Current
DRIVER AC SPECIFICATIONS
ADCLKOUT Clock Duty Cycle⁽⁴⁾
LCLKOUT Duty Cycle⁽⁴⁾
Data Setup Time⁽⁵⁾⁽⁶⁾
Data Hold Time⁽⁶⁾⁽⁷⁾
LVDS Outputs Rise/Fall Time⁽⁸⁾
LCLKOUT Rising Edge to ADCLKOUT Rising Edge⁽⁹⁾
ADCLKOUT Rising Edge to LCLKOUT Falling Edge⁽⁹⁾
ADCLKOUT Rising Edge to DATA OUT Transition⁽⁹⁾
Drivers Shorted Together
I_O = 2.5mA
I_O = 3.5mA
I_O = 4.5mA
I_O = 6.0mA
12
mA
45
50
55
%
40
50
60
%
0.35
ns
0.20
ns
400
ps
180
300
500
ps
230
ps
180
ps
0.33 0.60 0.86
ns
0.33 0.60 0.86
ns
–0.3
0
+0.3
ns
(1) The dc specifications refer to the condition where the LVDS outputs are not switching, but are permanently at a valid logic level 0 or 1.
(2) V_OS refers to the common-mode of OUT_P and OUT_N.
(3) Output capacitance inside the device, from either OUT_P or OUT_N to ground.
(4) Measured between zero crossings.
(5) DATA OUT (OUT_P – OUT_N) crossing zero to LCLKOUT (LCLK_P – LCLK_N) crossing zero.
(6) Data setup and hold time accounts for data-dependent skews, channel-to-channel mismatches, and effects of clock jitter in the device.
(7) LCLKOUT crossing zero to DATA OUT crossing zero.
(8) Measured from –100mV to +100mV on the differential output for rise time, and +100mV to –100mV for fall time.
(9) Measured between zero crossings.
SWITCHING CHARACTERISTICS
T_MIN = –40°C and T_MAX = +85°C. Typical values are at T_A = 25°C, clock frequency = maximum specified, 50% clock duty cycle,
AVDD = 3.3V, LVDD = 3.3V, –1dBFS, I_SET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless
otherwise noted.
PARAMETER
SWITCHING SPECIFICATIONS
t_SAMPLE
t_D(A) Aperture Delay⁽¹⁾
Aperture Jitter (uncertainty)
t_D(pipeline) Latency
t_PROP Propagation Delay⁽²⁾
MIN
TYP
MAX
UNITS
14.3
2
4
1
6.5
3
4.8
50
ns
6.5
ns
ps rms
Cycles
6.5
ns
(1) Rising edge of ADCLK to actual instant when data is sampled within the ADC.
(2) Falling edge of ADCLK to zero-crossing of rising edge of ADCLKOUT.
Copyright © 2004–2009, Texas Instruments Incorporated
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