ADS5273_14 Datasheet, PDF (2/33 Pages) Texas Instruments – 8-Channel, 12-Bit, 70MSPS Analog-to-Digital Converter

ADS5273
SBAS305D – JANUARY 2004 – REVISED JANUARY 2009 .............................................................................................................................................. www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION⁽¹⁾
PACKAGE
PRODUCT PACKAGE-LEAD⁽²⁾ DESIGNATOR
ADS5273
HTQFP-80
PFP
SPECIFIED
TEMPERATURE
RANGE
–40°C to +85°C
PACKAGE
MARKING
ADS5273IPFP
ORDERING
NUMBER
ADS5273IPFP
ADS5273IPFPT
TRANSPORT
MEDIA, QUANTITY
Tray, 96
Tape and Reel, 250
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document or see the TI
web site at www.ti.com.
(2) Thermal pad size: 4.69mm × 4.69mm (min), 6.20mm × 6.20mm (max).
ABSOLUTE MAXIMUM RATINGS⁽¹⁾
Analog Supply Voltage Range, AVDD
Output Driver Supply Voltage Range, LVDD
Voltage Between AVSS and LVSS
Voltage Between AVDD and LVDD
Voltages Applied to External REF Pins
All LVDS Data and Clock Outputs
Analog Input Pins⁽²⁾
Digital Input Pins, Set 1 (pins 69, 76-78)
Digital Input Pins, Set 2 (pins 16, 45)
Operating Free-Air Temperature Range, T_A
Lead Temperature, 1.6mm (1/16" from case for 10s)
Junction Temperature
Storage Temperature Range
–0.3V to +3.8V
–0.3V to +3.8V
–0.3V to +0.3V
–0.3V to +0.3V
–0.3V to +2.4V
–0.3V to +2.4V
–0.3V to min. [3.3V, (AVDD + 0.3V)]
–0.3V to min. [3.9V, (AVDD + 0.3V)]⁽³⁾
–0.3V to min. [3.9V, (LVDD + 0.3V)]⁽³⁾
–40°C to +85°C
+260°C
+105°C
–65°C to +150°C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
(2) The dc voltage applied on the input pins should not go below –0.3V. Also, the dc voltage should be limited to the lower of either 3.3V or
(AVDD + 0.3V). If the input can go higher than +3.3V, then a resistor greater than or equal to 25Ω should be added in series with each
of the input pins. Also, the duty cycle of the overshoot beyond +3.3V should be limited. The overshoot duty cycle can be defined either
as a percentage of the time of overshoot over a clock period, or over the entire device lifetime. For a peak voltage between +3.3V and
+3.5V, a duty cycle up to 10% is acceptable. For a peak voltage between +3.5V and +3.7V, the overshoot duty cycle should not exceed
1%. Any overshoot beyond +3.7V should be restricted to less than 0.1% duty cycle, and never exceed +3.9V.
(3) It is recommended that a series resistor of 1kΩ or greater be used if the digital input pins are tied to AVDD or LVDD.
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