DP83630SQE Datasheet, PDF (67/135 Pages) Texas Instruments – DP83630 Precision PHYTER™ - IEEE 1588 Precision Time Protocol Transceiver

DP83630
www.ti.com
SNLS335B – OCTOBER 2010 – REVISED APRIL 2013
8 Reset Operation
The DP83630 includes an internal power-on reset (POR) function and does not need to be explicitly reset
for normal operation after power up. If required during normal operation, the device can be reset by a
hardware or software reset.
8.1 HARDWARE RESET
A hardware reset is accomplished by applying a low pulse (TTL level), with a duration of at least 1 µs, to
the RESET_N pin. This will reset the device such that all registers will be reinitialized to default values and
the hardware configuration values will be re-latched into the device (similar to the power-up/reset
operation).
8.2 FULL SOFTWARE RESET
A full-chip software reset is accomplished by setting the RESET bit (bit 15) of the Basic Mode Control
Register (BMCR). The period from the point in time when the reset bit is set to the point in time when
software reset has concluded is approximately 1 µs.
The software reset will reset the device such that all registers will be reset to default values and the
hardware configuration values will be maintained. Software driver code must wait 3 µs following a software
reset before allowing further serial MII operations with the DP83630.
8.3 SOFT RESET
A partial software reset can be initiated by setting the SOFT_RESET bit (bit 9) in the PHYCR2 Register.
Setting this bit will reset all transmit and receive operations, but will not reset the register space. All
register configurations will be preserved. Register space will remain available following a soft reset.
8.4 PTP RESET
The entire PTP function, including the IEEE 1588 clock, associated logic, and PTP register space (with
two exceptions), can be reset via the PTP_RESET bit in the PTP_CTL register. The PTP_COC and
PTP_CLKSRC registers are not reset in order to preserve the nominal operation of the clock output.
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Reset Operation
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