DP83630SQE Datasheet, PDF (127/135 Pages) Texas Instruments – DP83630 Precision PHYTER™ - IEEE 1588 Precision Time Protocol Transceiver

DP83630
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SNLS335B – OCTOBER 2010 – REVISED APRIL 2013
10.7.3 PHY Status Frame Configuration Register 2 (PSF_CFG2), Page 6
This register provides configuration for the PHY Status Frame function. Specifically, the 16-bit value in this
register is used as the first 16-bits of the IP Source address for an IPv4 PHY Status Frame.
Table 10-66. PHY Status Frame Configuration Register 2 (PSF_CFG2), address 0x16
Bit
Bit Name
15:8
IP_SA_BYTE1
7:0
IP_SA_BYTE0
Default
0000 0000, RW
0000 0000, RW
Description
Second byte of IP source address:
This field contains the second byte of the IP source address.
First byte of IP source address:
This field contains the most significant byte of the IP source address.
10.7.4 PHY Status Frame Configuration Register 3 (PSF_CFG3), Page 6
This register provides configuration for the PHY Status Frame function. Specifically, the 16-bit value in this
register is used as the second 16-bits of the IP Source address for an IPv4 PHY Status Frame.
Table 10-67. PHY Status Frame Configuration Register 3 (PSF_CFG3), address 0x17
Bit
Bit Name
15:8
IP_SA_BYTE3
7:0
IP_SA_BYTE2
Default
0000 0000, RW
0000 0000, RW
Description
Fourth byte of IP source address:
This field contains the fourth byte of the IP source address.
Third byte of IP source address:
This field contains the third byte of the IP source address.
10.7.5 PHY Status Frame Configuration Register 4 (PSF_CFG4), Page 6
This register provides configuration for the PHY Status Frame function. Specifically, the 16-bit value in this
register is used to assist in computation of the IP checksum for an IPv4 PHY Status Frame.
Table 10-68. PHY Status Frame Configuration Register 4 (PTP_PKTSTS4), address 0x18
Bit
Bit Name
15:0
IP_CHKSUM
Default
0000 0000 0000
0000, RW
Description
IP Checksum:
This field contains a precomputed value ones-complement addition of all fixed
values in the IP Header. The device will add the Total Length and Identification
values to generate the final checksum.
10.7.6 PTP SFD Configuration Register (PTP_SFDCFG), Page 6
This register provides configuration to enable outputting the RX and TX Start-of-Frame (SFD) signals on
GPIO pins. Note that GPIO assignments are not exclusive.
Table 10-69. PTP SFD Configuration Register (PTP_SFDCFG), address 0x19
Bit
Bit Name
15:8
RESERVED
7:4
TX_SFD_GPIO
3:0
RX_SFD_GPIO
Default
0000 0000, RO
0000, RW
0000, RW
Description
Reserved: Writes ignored, Read as 0
TX SFD GPIO Select:
This field controls the GPIO output to which the TX SFD signal is assigned. Valid
values are 0 (disabled) or 1-12.
RX SFD GPIO Select:
This field controls the GPIO output to which the RX SFD signal is assigned. Valid
values are 0 (disabled) or 1-12.
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