DAC34SH84 Datasheet, PDF (67/77 Pages) Texas Instruments – Quad-Channel, 16-Bit, 1.5 GSPS Digital-to-Analog Converter (DAC)

DAC34SH84
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NCO CONFIGURATION
SLAS808B – FEBRUARY 2012 – REVISED JULY 2012
f_NCO = 122.88 MHz
f_{NCO_CLK} = 1474.56 MHz
freq = f_NCO × 2³² / 1228.8 = 357,913,941 = 0x1555 5555
phaseaddAB(31:0) and/or phaseaddCD(31:0) = 0x1555 5555
NCO SYNC = sif_sync
EXAMPLE START-UP SEQUENCE
STEP
1
2
3
4
5
6
7
READ/WRITE
N/A
N/A
N/A
N/A
Write
Write
Write
8
Write
9
Write
10
Write
11
Write
12
Write
13
Write
14
Write
15
Write
16
Write
17
Write
18
Write
19
Write
20
Write
21
Write
22
Write
23
Write
24
Write
25
Write
26
Write
27
Write
28
Write
29
Write
Table 10. Example Start-Up Sequence Description
ADDRESS
N/A
N/A
N/A
N/A
0x00
0x01
0x02
0x03
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
VALUE
N/A
N/A
N/A
N/A
0xF19F
0x040E
0x7052
0xA000
0xD8FF
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0x5555
0x1555
0x5555
0x1555
0x2C50
0x20F4
0x7010
0x0800
DESCRIPTION
Set TXENA low
Power up the device
Apply LVPECL DACCLKP/N for PLL reference clock
Toggle RESETB pin
QMC offset and correction enabled, 2x int, FIFO enabled, Alarm enabled,
clock divider sync enabled, inverse sinc filter enabled.
Single parity enabled, FIFO alarms enabled (2 away, 1 away, and collision).
Output shut-off when DACCLK gone, DATACLK gone, and FIFO collision.
Mixer block with NCO enabled, twos complement.
Output current set to 20 mAFS with internal reference and 1.28-kΩ R_BIAS
resistor.
Un-mask FIFO collision, DACCLK-gone, and DATACLK-gone alarms to the
Alarm output.
Program the desired channel A QMC offset value. (Causes auto-sync for
QMC AB-channels offset block)
Program the desired FIFO offset value and channel B QMC offset value.
Program the desired channel C QMC offset value. (Causes auto-sync for
QMC CD-channels offset block)
Program the desired channel D QMC offset value.
Program the desired channel A QMC gain value.
Coarse mixer mode not used. Program the desired channel B QMC gain
value.
Program the desired channel B QMC gain value.
Program the desired channel C QMC gain value.
Program the desired channel AB QMC phase value. (Causes Auto-Sync
QMC AB-Channels Correction Block)
Program the desired channel CD QMC phase value. (Causes Auto-Sync for
the QMC CD-Channels Correction Block)
Program the desired channel AB NCO phase offset value. (Causes Auto-
Sync for Channel AB NCO Mixer)
Program the desired channel CD NCO phase offset value. (Causes Auto-
Sync for Channel CD NCO Mixer)
Program the desired channel AB NCO frequency value
Program the desired channel AB NCO frequency value
Program the desired channel CD NCO frequency value
Program the desired channel CD NCO frequency value
PLL enabled, PLL N-dividers sync enabled, single charge pump, prescaler =
2.
M = 32, N = 16, PLL VCO bias tune = "01"
PLL VCO coarse tune = 28
Internal reference
Copyright © 2012, Texas Instruments Incorporated
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