DAC34SH84 Datasheet, PDF (45/77 Pages) Texas Instruments – Quad-Channel, 16-Bit, 1.5 GSPS Digital-to-Analog Converter (DAC)

DAC34SH84
www.ti.com
Register
config0
config32
Control Bits
fifo_ena
syncsel_fifoout(3:0)
SLAS808B – FEBRUARY 2012 – REVISED JULY 2012
FIFO Mode
fifo_ena
Dual Sync Sources
1
Single Sync
Source
1
Bypass
0
Table 4. FIFO Operation Modes
Bit 3: sif_sync
0
0
X
config0 and config32 FIFO Bits
syncsel_fifoout
Bit 2: OSTR
Bit 1: ISTR
1
0
0
1 or 0 Depends on the sync
source
X
X
Bit 0: SYNC
0
1 or 0 Depends on the
sync source
X
DUAL-SYNC-SOURCES MODE
This is the recommended mode of operation for those applications that require precise control of the output
timing. In Dual Sync Sources mode, the FIFO write and read pointers are reset independently. The FIFO write
pointer is reset using the LVDS ISTR or SYNC signal, and the FIFO read pointer is reset using the LVPECL
OSTR signal. This allows LVPECL OSTR signal to control the phase of the output for either a single chip or
multiple chips. Multiple devices can be fully synchronized in this mode.
SINGLE-SYNC-SOURCE MODE
In single-sync-source mode, the FIFO write and read pointers are reset from the same source, either LVDS ISTR
or LVDS SYNC signal. This mode has a possibility of up to 2 DAC clocks offset between the multiple DAC
outputs. Applications requiring exact output timing control need dual-sync-sources mode instead of single-sync-
source mode. A single rising edge for FIFO and clock divider sync is recommended. Periodic sync signal is not
recommended due to the non-deterministic latency of the sync signal through the clock domain transfer.
In this mode, there is a chance for FIFO pointers 2 away alarm (or possibly 1 away alarm) to occur at initial setup
or syncing. This is the result of single-sync-source mode having 0 to 3 address location slip, which is caused by
the asynchronous handoff of the sync signal occurring between the DATACLK zone and the DACCLK zone. The
asynchronous relationship between the clock domains means there could be a slip (from nominal) in the READ
and WRITE pointers at initial syncing. For example, with the default programming of FIFO offset of 4, the actual
FIFO offset may be 3, 2, or in some instances, 1. Please note that in this mode, the nominal address location slip
is 0 with the possibility getting less for each increase in slip amount. Also, the slip does not continue to occur as
the device functions, but the READ/WRITE pointers may not be at optimal settings. If an alarm occurs:
1. Adjust the FIFO offset accordingly and resynchronize the FIFO, data formatter, etc., such that there are no
alarms reported or at least only the 2-away alarm is reported.
2. The FIFO collision alarm is a warning of the system, because the read and write processes occur at the
same pointer. However, the FIFO 1-away and 2-away alarms are informational for the system designer. The
important thing for these two alarms is that the alarm should not get closer to collision during normal
operation. If the 1-away alarm or collision alarm starts to occur, it is a warning to check for system errors.
The system should have an interrupt or algorithm to fix the error and resynchronize the alarm appropriately.
BYPASS MODE
In FIFO bypass mode, the FIFO block is not used. As a result, the input data is handed off from the DATACLK to
the DACCLK domain without any compensation. In this mode, the relationship between DATACLK and DACCLK
is critical and used as a synchronizing mechanism for the internal logic. Due to this constraint, this mode is not
recommended. In bypass mode, the pointers have no effect on the data path or handoff.
CLOCKING MODES
The DAC34SH84 has a dual-clock setup in which a DAC clock signal is used to clock the DAC cores and internal
digital logic, and a separate DATA clock is used to clock the input LVDS receivers and FIFO input. The
DAC34SH84 DAC clock signal can be sourced directly or generated through an on-chip low-jitter phase-locked
loop (PLL).
Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): DAC34SH84
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