TM4C1231E6PZ Datasheet, PDF (66/1173 Pages) Texas Instruments – Tiva™ TM4C1231E6PZ Microcontroller

The Cortex-M4F Processor
Table 2-2. Processor Register Map (continued)
Offset Name
Type
Reset
Description
-
R12
-
SP
-
LR
-
PC
-
PSR
-
PRIMASK
-
FAULTMASK
-
BASEPRI
-
CONTROL
-
FPSC
RW
-
Cortex General-Purpose Register 12
RW
-
Stack Pointer
RW
0xFFFF.FFFF Link Register
RW
-
Program Counter
RW
0x0100.0000 Program Status Register
RW
0x0000.0000 Priority Mask Register
RW
0x0000.0000 Fault Mask Register
RW
0x0000.0000 Base Priority Mask Register
RW
0x0000.0000 Control Register
RW
-
Floating-Point Status Control
See
page
67
68
69
70
71
75
76
77
78
80
2.3.4
Register Descriptions
This section lists and describes the Cortex-M4F registers, in the order shown in Figure
2-3 on page 65. The core registers are not memory mapped and are accessed by register name
rather than offset.
Note: The register type shown in the register descriptions refers to type during program execution
in Thread mode and Handler mode. Debug access can differ.
66
June 12, 2014
Texas Instruments-Production Data