TM4C1231E6PZ Datasheet, PDF (605/1173 Pages) Texas Instruments – Tiva™ TM4C1231E6PZ Microcontroller

Tiva^™ TM4C1231E6PZ Microcontroller
Register 22: DMA Channel Interrupt Status (DMACHIS), offset 0x504
Each bit of the DMACHIS register represents the corresponding µDMA channel. A bit is set when
that μDMA channel causes a completion interrupt. The bits are cleared by a writing a 1.
Note:
When transfers are performed from a FIFO of the UART or SSI using the μDMA, and any
interrupt is generated from the UART or SSI, the module's status bit in the DMACHIS register
must be checked at the end of the interrupt service routine. If the status bit is set, clear the
interrupt by writing a 1 to it.
DMA Channel Interrupt Status (DMACHIS)
Base 0x400F.F000
Offset 0x504
Type RW1C, reset 0x0000.0000
31
30
29
28
27
26
Type RW1C
Reset
0
RW1C
0
RW1C
0
RW1C
0
RW1C
0
RW1C
0
25
RW1C
0
24
23
CHIS[n]
RW1C
0
RW1C
0
22
RW1C
0
21
RW1C
0
20
RW1C
0
19
RW1C
0
18
RW1C
0
17
RW1C
0
16
RW1C
0
15
Type RW1C
Reset
0
14
RW1C
0
13
RW1C
0
12
RW1C
0
11
RW1C
0
10
RW1C
0
9
RW1C
0
8
7
CHIS[n]
RW1C
0
RW1C
0
6
RW1C
0
5
RW1C
0
4
RW1C
0
3
RW1C
0
2
RW1C
0
1
RW1C
0
0
RW1C
0
Bit/Field
31:0
Name
CHIS[n]
Type
Reset Description
RW1C 0x0000.0000 Channel [n] Interrupt Status
Value Description
0 The corresponding μDMA channel has not caused an interrupt.
1 The corresponding μDMA channel caused an interrupt.
This bit is cleared by writing a 1 to it.
June 12, 2014
605
Texas Instruments-Production Data