ADS54J66 Datasheet, PDF (66/82 Pages) Texas Instruments – Quad-Channel, 14-Bit, 500-MSPS ADC with Integrated DDC

ADS54J66
SBAS745A – NOVEMBER 2015 – REVISED DECEMBER 2015
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7.6.3.7.14 Register 20h (address = 20h) [reset = 0h], JESD Digital Page (6900h)
Figure 135. Register 20h
7
6
5
4
3
2
1
0
HC[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 66. Register 20h Field Descriptions
Bit Name
7-0 HC[7:0]
Type
R/W
Reset
0h
Description
These bits set the high resolution counter value. When programming
HC[27:0], first program HC[7:0], then HC[15:8], then HC[23:16], and then
HC[27:24] in the same order.
7.6.3.7.15 Register 21h (address = 21h) [reset = 0h], JESD Digital Page (6900h)
Figure 136. Register 21h
7
6
5
4
OUTPUT CHA MUX SEL
OUTPUT CHB MUX SEL
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
3
2
OUTPUT CHC MUX SEL
R/W-0h
1
0
OUTPUT CHD MUX SEL
R/W-0h
Table 67. 21h Field Descriptions
Bit Name
Type
Reset
7-6 OUTPUT CHA MUX SEL R/W
0h
5-4 OUTPUT CHB MUX SEL R/W
0h
3-2 OUTPUT CHC MUX SEL R/W
0h
1-0 OUTPUT CHD MUX SEL R/W
0h
Description
SERDES lane swap with ch B.
00 = Ch A is output on lane DA
10 = Ch A is output on lane DB
01, 11 = Do not use
SERDES lane swap with ch A.
00 = Ch B is output on lane DB
10 = Ch B is output on lane DA
01, 11 = Do not use
SERDES lane swap with ch D.
00 = Ch C is output on lane DC
10 = Ch C is output on lane DD
01, 11 = Do not use
SERDES lane swap with ch C.
00 = Ch D is output on lane DD
10 = Ch D is output on lane DC
01, 11 = Do not use
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