ADS54J66 Datasheet, PDF (10/82 Pages) Texas Instruments – Quad-Channel, 14-Bit, 500-MSPS ADC with Integrated DDC

ADS54J66
SBAS745A – NOVEMBER 2015 – REVISED DECEMBER 2015
www.ti.com
6.7 Digital Characteristics
typical values are at T_A = 25°C, full temperature range is from T_MIN = –40°C to T_MAX = 85°C, ADC sampling rate = 500 MSPS,
50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
DIGITAL INPUTS (RESET, SCLK, SEN, SDIN, PDN)⁽¹⁾
V_IH
High-level input voltage
V_IL
Low-level input voltage
I_IH
High-level input current
All digital inputs support 1.2-V and 1.8-V logic levels
All digital inputs support 1.2-V and 1.8-V logic levels
SEN
RESET, SCLK, SDIN, PDN
I_IL
Low-level input current
SEN
RESET, SCLK, SDIN, PDN
DIGITAL INPUTS (SYSREFP, SYSREFM, SYNCbABM, SYNCbABP, SYNCbCDM, SYNCbCDP)
V_D
Differential input voltage
V_{(CM_DIG)} Common-mode voltage for SYSREF
DIGITAL OUTPUTS (SDOUT, PDN)
V_OH
High-level output voltage
V_OL
Low-level output voltage
DIGITAL OUTPUTS (JESD204B Interface: DxP, DxM)⁽²⁾
V_OD
Output differential voltage
V_OC
Output common-mode voltage
Transmitter short-circuit current
With default swing setting
Transmitter pins shorted to any voltage between
–0.25 V and 1.45 V
z_os
Single-ended output impedance
Output capacitance
Output capacitance inside the device,
from either output to ground
MIN
0.8
0.35
DVDD –
0.1
–100
TYP
0
100
50
0
0.45
1.3
DVDD
700
450
50
2
MAX UNIT
V
0.4
V
µA
µA
1.4
V
V
V
0.1
V
mV_PP
mV
100
mA
Ω
pF
(1) The RESET, SCLK, SDATA, and PDN pins have a 20-kΩ (typical) internal pulldown resistor to ground, and the SEN pin has a 20-kΩ
(typical) pull up resistor to IOVDD.
(2) 50-Ω, single-ended external termination to IOVDD.
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