TPS65986 Datasheet, PDF (65/109 Pages) Texas Instruments – USB Type-C and USB PD Controller and Power Switch

www.ti.com
Device Functional Modes (continued)
Region Pointer (RPTR)
Low Header
4 kB
App Code Offset (AOFF)
Region Pointer (RPTR)
High Header
4 kB
App Code Offset (AOFF)
Configuration ID
RESERVED
Configuration Size (CSIZE)
Bin Size
Bin CRC
RESERVED
Application Code
64 kB
TPS65986
SLVSD13A – OCTOBER 2015 – REVISED NOVEMBER 2015
0x000000
0x000004
0x000FFC
0x001000
0x001004
0x001FFC
0x002000
RPTR+AOFF
RPTR+AOFF+4
RPTR+AOFF+8
RPTR+AOFF+12
RPTR+AOFF+16
RPTR+AOFF+20
RPTR+AOFF+CSIZE
Figure 63. Flash Memory Organization
There are two 4 kB header blocks starting at address 0x000000h. The Low Header 4 kB block is at address
0x000000h and the High Header 4 kB block is at 0x001000h. Each header contains a Region Pointer (RPTR)
that holds the address of the physical location in memory where the low region application code resides. Each
also contains an Application Code Offset (AOFF) that contains the physical offset inside the region where the
TPS65986 application code resides. The TPS65986 firmware physical location in memory is RPTR + AOFF. The
first sections of the TPS65986 application code contain device configuration settings. This configuration
determines the devices default behavior after power-up and can be customized using the TPS65986
Configuration Tool. These pointers may be valid or invalid. The Flash Read flow handles reading and
determining whether a region is valid and contains good application code.
8.4.6 Flash Memory Read
The TPS65986 first attempts to load application code from the low region of the attached flash memory. If any
part of the read process yields invalid data, the TPS65986 will abort the low region read and attempt to read from
the high region. If both regions contain invalid data the device carries out the Invalid Memory flow. Figure 64
shows the flash memory read flow.
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS65986
Submit Documentation Feedback
65