TM4C1232E6PM Datasheet, PDF (643/1171 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1232E6PM Microcontroller
Table 10-5. 16-Bit Timer With Prescaler Configurations (continued)
Prescale (8-bit value)
# of Timer Clocks (Tc)^a
Max Time
11111110
255
208.896
11111111
256
209.7152
a. Tc is the clock period.
Units
ms
ms
The following table shows a variety of configurations for a 32-bit free-running timer using the prescaler
while configured in 32/64-bit mode. All values assume an 80-MHz clock with Tc=12.5 ns (clock
period).
Table 10-6. 32-Bit Timer (configured in 32/64-bit mode) With Prescaler Configurations
Prescale (16-bit value)
# of Timer Clocks (Tc)^a
Max Time
Units
0x0000
1
53.687
s
0x0001
2
107.374
s
0x0002
3
214.748
s
------------
0xFFFD
0xFFFE
0xFFFF
--
65534
65535
65536
--
0.879
1.759
3.518
--
10⁶ s
10⁶ s
10⁶ s
a. Tc is the clock period.
10.3.2.2
Real-Time Clock Timer Mode
In Real-Time Clock (RTC) mode, the concatenated versions of the Timer A and Timer B registers
are configured as an up-counter. When RTC mode is selected for the first time after reset, the
counter is loaded with a value of 0x1. All subsequent load values must be written to the GPTM
Timer n Interval Load (GPTMTnILR) registers (see page 688). If the GPTMTnILR register is loaded
with a new value, the counter begins counting at that value and rolls over at the fixed value of
0xFFFFFFFF. Table 10-7 on page 643 shows the values that are loaded into the timer registers when
the timer is enabled.
Table 10-7. Counter Values When the Timer is Enabled in RTC Mode
Register
GPTMTnR
GPTMTnV
GPTMTnPS
GPTMTnPV
Count Down Mode
Not available
Not available
Not available
Not available
Count Up Mode
0x1
0x1
Not available
Not available
The input clock on a CCP0 input is required to be 32.768 KHz in RTC mode. The clock signal is
then divided down to a 1-Hz rate and is passed along to the input of the counter.
When software writes the TAEN bit in the GPTMCTL register, the counter starts counting up from
its preloaded value of 0x1. When the current count value matches the preloaded value in the
GPTMTnMATCHR registers, the GPTM asserts the RTCRIS bit in GPTMRIS and continues counting
until either a hardware reset, or it is disabled by software (clearing the TAEN bit). When the timer
value reaches the terminal count, the timer rolls over and continues counting up from 0x0. If the
RTC interrupt is enabled in GPTMIMR, the GPTM also sets the RTCMIS bit in GPTMMIS and
generates a controller interrupt. The status flags are cleared by writing the RTCCINT bit in GPTMICR.
In this mode, the GPTMTnR and GPTMTnV registers always have the same value.
June 12, 2014
643
Texas Instruments-Production Data