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TMS320VC5510_14 Datasheet, PDF (64/90 Pages) Texas Instruments – Fixed-Point Digital Signal Processors | |||
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Electrical Specifications
5.8 HOLD and HOLDA Timings
Table 5â11 and Table 5â12 assume testing over recommended operating conditions (see Figure 5â14).
Table 5â11. HOLD and HOLDA Timing Requirements
VC5510/5510A-160
NO.
VC5510/5510A-200
MIN MAX
H1 tsu(HOLDH-COH)
Setup time, HOLD high before CLKOUT highâ
7
â HOLD is synchronized internally. If the setup time shown is not met, HOLD will be recognized on the next clock cycle.
UNIT
ns
Table 5â12. HOLD and HOLDA Switching Characteristicsâ¡
VC5510/5510A-160
NO.
PARAMETER
VC5510/5510A-200 UNIT
MIN
MAX
H2 tR(COH-BHZ)
Response time, CLKOUT high to EMIF Bus high impedance (HZ)¶
4P
§ ns
H3 tR(COH-HOLDAL) Response time, CLKOUT high to HOLDA low
5Pâ1
ns
H4 tR(COH-HOLDAH) Response time, CLKOUT high to HOLDA high
H5 tR(COH-BLZ)
Response time, CLKOUT high to EMIF Bus low impedance (LZ) (active)¶
4Pâ1
4Pâ1
4P+5 ns
4P+5 ns
â¡ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
§ All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay
time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
¶ EMIF Bus consists of CE[3:0], BE[3:0], D[31:0], A[21:0], ARE, AOE, AWE, SSADS, SSOE, SSWE, CLKMEM, SDA10, SDRAS, SDCAS, and
SDWE.
CLKOUT
HOLD
HOLDA
EMIF BUSâ
H1
H3
H2
H1
H4
H5
â EMIF Bus consists of CE[3:0], BE[3:0], D[31:0], A[21:0], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, SDWE, and
CLKMEM.
Figure 5â14. HOLD/HOLDA Timing
64 SPRS076O
June 2000 â Revised September 2007
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