TMS320VC5510_14 Datasheet, PDF (45/90 Pages) Texas Instruments – Fixed-Point Digital Signal Processors

Functional Overview
3.5.1 IFR and IER Registers
The Interrupt Enable Registers (IER0 and IER1) control which interrupts will be masked or enabled during
normal operation. The Interrupt Flag Registers (IFR0 and IFR1) contain flags that indicate interrupts that are
currently pending.
The Debug Interrupt Enable Registers (DBIER0 and DBIER1) are used only when the CPU is halted in the
real-time emulation mode. If the CPU is running in real-time mode, the standard interrupt processing (IER0/1)
is used and DBIER0/1 are ignored.
A maskable interrupt enabled in a DBIER0/1 is defined as a time-critical interrupt. When the CPU is halted
in the real-time mode, the only interrupts that are serviced are time-critical interrupts that are also enabled in
an interrupt enable register (IER0 or IER1)
Write the DBIER0/1 to enable or disable time-critical interrupts. To enable an interrupt, set its corresponding
bit. To disable an interrupt, clear its corresponding bit. Note that DBIER0/1 are not affected by a software reset
instruction or by a DSP hardware reset. Initialize these registers before using the real-time emulation mode.
The bit layouts of these registers for each interrupt are shown in Figure 3−7.
15
DMAC5
14
DMAC4
13
XINT2
12
RINT2
11
INT3
10
DSPINT
9
DMAC1
8
Reserved
7
XINT1
6
RINT1
5
RINT0
4
TINT0
3
INT2
2
1
0
INT0
Reserved
Figure 3−7. IFR0, IER0, DBIFR0, and DBIER0 Bit Locations
The IFR1 (Interrupt Flag Register 1) and IER1 (Interrupt Enable Register 1) bit layouts are shown in
Figure 3−8.
15
11
10
9
8
Reserved
RTOS
DLOG
BERR
7
INT5
6
TINT1
5
DMAC3
4
DMAC2
3
INT4
2
DMAC0
1
XINT0
0
INT1
Figure 3−8. IFR1, IER1, DBIFR1, and DBIER1 Bit Locations
3.5.2 Interrupt Timing
The external interrupts (NMI and INTx) are automatically synchronized to the CPU. The interrupt inputs are
sampled on the falling edges of the CPU clock. A sequence on the interrupt pin of 1-0-0-0 on consecutive
cycles is required for an interrupt to be detected. Therefore, the minimum low pulse duration on the external
interrupts on the 5510/5510A is three CPU clock periods.
June 2000 − Revised September 2007
SPRS076O
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