ADC12D1620QML-SP Datasheet, PDF(64/82 Page) Texas Instruments – 12-Bit, Single Or Dual, 3200- or 1600-MSPS RF Sampling Analog-to-Digital Converter (ADC)

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

ADC12D1620QML-SP Datasheet, PDF (64/82 Pages) Texas Instruments – 12-Bit, Single Or Dual, 3200- or 1600-MSPS RF Sampling Analog-to-Digital Converter (ADC)

◁

ADC12D1620QML-SP

SNAS717 â APRIL 2017

www.ti.com

Similarly, if the Q channel is powered-down (that is, PDQ is logic-high), the DQ data output pins, DCLKQ and

ORQ, may be left not connected.

8.1.4 Synchronizing Multiple ADC12D1620 Devices in a System

The ADC12D1620 has two features to assist the user with synchronizing multiple ADCs in a system: AutoSync

and DCLK reset. The AutoSync feature is new and designates one ADC12D1620 as the master ADC and other

ADC12D1620 devices in the system as slave ADCs. The DCLK reset feature performs the same function as the

AutoSync feature, but is the first-generation solution to synchronizing multiple ADCs in a system; it is disabled by

default. For applications in which there are multiple master and slave ADC12D1620 devices in a system,

AutoSync may be used to synchronize the slave ADC12D1620 devices to each respective master ADC12D1620,

and the DCLK reset may be used to synchronize the master ADC12D1620 devices to each other.

If the AutoSync or DCLK reset feature is not used, see Table 30 for recommendations about terminating unused

pins.

Table 30. Unused AutoSync and DCLK Reset Pin Recommendation

PIN(s)

RCLK+, RCLKâ

RCOUT1+, RCOUT1â

RCOUT2+, RCOUT2â

DCLK_RST+

DCLK_RST-

UNUSED TERMINATION

Do not connect.

Connect to GND with a 1-kâ¦ resistor.

Connect to VA with a 1-kâ¦ resistor.

8.1.4.1 AutoSync Feature

AutoSync is a new feature which continuously synchronizes the outputs of multiple ADC12D1620 devices in a

system. It may be used to synchronize the DCLK and data outputs of one or more slave ADC12D1620 devices to

one master ADC12D1620. Several advantages of this feature include: no special synchronization pulse required,

any upset in synchronization is recovered upon the next DCLK cycle, and the master/slave ADC12D1620

devices may be arranged as a binary tree so that any upset quickly propagates out of the system.

An example system is shown in Figure 48, which consists of one master ADC and two slave ADCs. For

simplicity, only one DCLK is shown; in reality, there is DCLKI and DCLKQ, but they are always in phase with one

another.

Slave 1

RCOut1

ADC12D1600/1000RF

RCOut2

DCLK

Slave 2

RCOut1

ADC12D1600/1000RF

RCOut2

DCLK

Master

RCOut1

ADC12D1600/1000RF

RCOut2

DCLK

CLK

Figure 48. AutoSync Example

Submit Documentation Feedback

Product Folder Links: ADC12D1620QML-SP

▷