ADC12D1620QML-SP Datasheet, PDF (13/82 Pages) Texas Instruments – 12-Bit, Single Or Dual, 3200- or 1600-MSPS RF Sampling Analog-to-Digital Converter (ADC)

ADC12D1620QML-SP
www.ti.com
SNAS717 – APRIL 2017
Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)⁽¹⁾
Input current at any pin except VinI+, VinI–, VinQ+, or VinQ–⁽⁴⁾
CLK+, CLK– voltage
Differential CLK amplitude
V_CMI common-mode input voltage
MIN
0
0.4
V_CMO – 150
MAX
±50
V_A
2
V_CMO + 150
UNIT
mA
V
V_P-P
mV
(4) When the input voltage at any pin exceeds the power supply limits, the current at that pin must be limited to 50 mA. In addition,
overvoltage at a pin must adhere to maximum voltage limits. Simultaneous overvoltage at multiple pins requires adherence to the
maximum package power dissipation limits, which are calculated using the JEDEC JESD51-7 thermal model. Higher dissipation may be
possible based on customer-specific thermal situations and specified thermal package resistances from junction to case.
6.4 Thermal Information
THERMAL METRIC⁽¹⁾⁽²⁾
ADC12D1620QML-SP
NAA (CCGA)
376 PINS
R_θJA
R_θJC(top)
R_θJB
ψ_JT
ψ_JB
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
13.1
5.0
5.1
2.6
4.7
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics
(2) Solder process specifications in Board Mounting Recommendation.
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
6.5 Converter Electrical Characteristics: Static Converter Characteristics
The following specifications apply after calibration for V_A = V_DR = V_TC = V_E = 1.9 V; I and Q channels AC-coupled, FSR pin =
high; C_L = 10-pF; differential AC-coupled sine wave input clock, f_CLK = 1.6 GHz at 0.5 V_P-P with 50% duty cycle; V_BG = floating;
non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2
demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on.⁽¹⁾⁽²⁾
PARAMETER
TEST CONDITIONS
SUB-GROUPS
MIN TYP⁽³⁾
MAX UNIT
INL
Integral non-linearity
DC-coupled, 1 MHz sine wave over-
ranged
[1, 2, 3]
–7.5
±2.5
7.5 LSB
DNL
Differential non-linearity
DC-coupled, 1 MHz sine wave over-
ranged
[1, 2, 3]
–1.35
±0.5
1.35 LSB
Resolution with no
missing codes
[1, 2, 3]
12 bits
V_OFF
V_OFF_ADJ
Offset error
Input offset adjustment
range
Extended control mode
8
LSB
±45
mV
(1) The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this
device.
V_A
I/O
TO INTERNAL
CIRCUITRY
GND
(2) To ensure accuracy, it is required that V_A, V_TC, V_E and V_DR be well bypassed. Each supply pin must be decoupled with separate bypass
capacitors.
(3) Typical figures are at T_A = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average
outgoing quality level (AOQL).
Copyright © 2017, Texas Instruments Incorporated
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