TMS320C542PGE2-40 Datasheet, PDF (63/118 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999
internal oscillator with external crystal
The internal oscillator is enabled by selecting the appropriate clock mode at reset (this is device dependent –
see PLL section) and connecting a crystal or ceramic resonator across X1 and X2/CLKIN. The CPU clock
frequency is one-half the crystal’s oscillation frequency following reset. After reset, the clock mode of the devices
with the software PLL can also be changed to divide-by-four.
The crystal should be in fundamental mode operation and parallel resonant with an effective series resistance
of 30ohms and power dissipation of 1 mW. The connection of the required circuit, consisting of the crystal and
two load capacitors, is shown in Figure 13. The load capacitors, C₁ and C₂, should be chosen such that the
equation below is satisfied. C_L in the equation is the load specified for the crystal.
C_L
+
C₁C₂
(C₁ ) C₂)
recommended operating conditions (see Figure 13)
’C54x-40
’LC54x-40
’LC54x-50
’54x-66
UNIT
MIN NOM MAX MIN NOM MAX MIN NOM MAX
fx
Input clock frequency
10†
20‡ 10†
20‡ 10†
20‡
MHz
† _{This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies}
approaching 0 Hz.
‡ _{It is recommended that the PLL clocking option be used for maximum frequency operation.}
X1
C1
X2/CLKIN
Crystal
C2
Figure 13. Internal Divide-by-Two Clock Option With External Crystal
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