TMS320C542PGE2-40 Datasheet, PDF (33/118 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999
software-programmable PLL (’545A, ’546A, ’548, and ’549) (continued)
Bits 15 –12 PLLMUL. PLL multiplier. Defines the frequency multiplier in conjunction with PLLDIV and
PLLNDIV, as shown in Table 5.
Bit 11
PLLDIV. PLL divider. Defines the frequency multiplier in conjunction with PLLMUL and PLLNDIV,
as shown in Table 5.
0 = an integer multiply factor is used.
1 = a non-integer multiply factor is used.
Bits 10 –3
PLLCOUNT. PLL counter value. Specifies the number of input clock cycles (in increments of
16 cycles) for the PLL lock timer to count before the PLL begins clocking the processor after the
PLL is started. The PLL counter is a down-counter, which is driven by the input clock divided
by 16; therefore, for every 16 input clocks, the PLL counter decrements by one.
The PLL counter can be used to ensure that the processor is not clocked until the PLL is locked,
so that only valid clock signals are sent to the device.
Bit 2
PLLON/OFF. PLL on/off. Enables or disables the PLL part of the clock generator in conjunction
with the PLLNDIV bit. Note that PLLON/OFF and PLLNDIV can both force the PLL to run; when
PLLON/OFF is high, the PLL runs independently of the state of PLLNDIV.
Bit 1
Bit 0
PLLON/OFF
0
1
0
1
PLLNDIV
0
0
1
1
PLL STATE
Off
On
On
On
PLLNDIV. PLL clock generator select. Determines whether the clock generator works in PLL
mode or in divider (DIV) mode, thereby defining the frequency multiplier in conjunction with
PLLMUL and PLLDIV.
0 = Divider mode is used
1 = PLL mode is used
PLLSTATUS. PLL status. Indicates the mode in which the clock generator is operating.
0 = DIV mode
1 = PLL mode
Table 5. PLL Multiplier Ratio as a Function of PLLNDIV, PLLDIV, and PLLMUL
PLLNDIV
0
0
1
1
1
1
† _{CLKOUT = CLKIN x multiplier}
PLLDIV
x
x
0
0
1
1
PLLMUL
0 – 14
15
0 – 14
15
0 or even
odd
MULTIPLIER†
0.5
0.25
PLLMUL + 1
Reserved
(PLLMUL + 1) B 2
PLLMUL B 4
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