ADC12D1800 Datasheet, PDF (63/84 Pages) National Semiconductor (TI) – 12-Bit, Single 3.6 GSPS ADC

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ADC12D1800
SNAS500P – MAY 2010 – REVISED JULY 2015
6.1.4.2 DCLK Reset Feature
The DCLK reset feature is available via ECM, but it is disabled by default. DCLKI and DCLKQ are always
synchronized, by design, and do not require a pulse from DCLK_RST to become synchronized.
The DCLK_RST signal must observe certain timing requirements, which are shown in Figure 4-6 of the
Timing Diagrams. The DCLK_RST pulse must be of a minimum width and its deassertion edge must
observe setup and hold times with respect to the CLK input rising edge. These timing specifications are
listed as t_PWR, t_SR and t_HR and may be found in Section 4.13.
The DCLK_RST signal can be asserted asynchronously to the input clock. If DCLK_RST is asserted, the
DCLK output is held in a designated state (logic-high) in Demux Mode; in Non-Demux Mode, the DCLK
continues to function normally. Depending upon when the DCLK_RST signal is asserted, there may be a
narrow pulse on the DCLK line during this reset event. When the DCLK_RST signal is de-asserted, there
are t_{SYNC_DLY} CLK cycles of systematic delay and the next CLK rising edge synchronizes the DCLK output
with those of other ADC12D1800s in the system. For 90° Mode (DDRPh = logic-high), the synchronizing
edge occurs on the rising edge of CLK, 4 cycles after the first rising edge of CLK after DCLK_RST is
released. For 0° Mode (DDRPh = logic-low), this is 5 cycles instead. The DCLK output is enabled again
after a constant delay of t_OD.
For both Demux and Non-Demux Modes, there is some uncertainty about how DCLK comes out of the
reset state for the first DCLK_RST pulse. For the second (and subsequent) DCLK_RST pulses, the DCLK
will come out of the reset state in a known way. Therefore, if using the DCLK Reset feature, it is
recommended to apply one "dummy" DCLK_RST pulse before using the second DCLK_RST pulse to
synchronize the outputs. This recommendation applies each time the device or channel is powered-on.
When using DCLK_RST to synchronize multiple ADC12D1800s, it is required that the Select Phase bits in
the Control Register (Addr: Eh, Bits 3,4) be the same for each Master ADC12D1800.
6.1.5 Recommended System Chips
TI recommends these other chips including temperature sensors, clocking devices, and amplifiers in order
to support the ADC12D1800 in a system design.
6.1.5.1 Temperature Sensor
The ADC12D1800 has an on-die temperature diode connected to pins Tdiode+/- which may be used to
monitor the die temperature. TI also provides a family of temperature sensors for this application which
monitor different numbers of external devices, see Table 6-5.
Table 6-5. Temperature Sensor Recommendation
NUMBER OF EXTERNAL
DEVICES MONITORED
1
2
4
RECOMMENDED TEMPERATURE
SENSOR
LM95235
LM95213
LM95214
The temperature sensor (LM95235/13/14) is an 11-bit digital temperature sensor with a 2-wire System
Management Bus (SMBus) interface that can monitor the temperature of one, two, or four remote diodes
as well as its own temperature. It can be used to accurately monitor the temperature of up to one, two, or
four external devices such as the ADC12D1800, a FPGA, other system components, and the ambient
temperature.
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