ADC12D1800 Datasheet, PDF (44/84 Pages) National Semiconductor (TI) – 12-Bit, Single 3.6 GSPS ADC

ADC12D1800
SNAS500P – MAY 2010 – REVISED JULY 2015
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5.5.1.1.2 Non-Demultiplexed Mode Pin (NDM)
The Non-Demultiplexed Mode (NDM) Pin selects whether the ADC12D1800 is in Demux Mode (logic-low)
or Non-Demux Mode (logic-high). In Non-Demux Mode, the data from the input is produced at the
sampled rate at a single 12-bit output bus. In Demux Mode, the data from the input is produced at half the
sampled rate at twice the number of output buses. For Non-DES Mode, each I- or Q-channel will produce
its data on one or two buses for Non-Demux or Demux Mode, respectively. For DES Mode, the selected
channel will produce its data on two or four buses for Non-Demux or Demux Mode, respectively.
This feature is pin-controlled only and remains active during both Non-ECM and ECM. See Section 5.4.2
for more information.
5.5.1.1.3 Dual Data Rate Phase Pin (DDRPh)
The Dual Data Rate Phase (DDRPh) Pin selects whether the ADC12D1800 is in 0° Mode (logic-low) or
90° Mode (logic-high). The Data is always produced in DDR Mode on the ADC12D1800. The Data may
transition either with the DCLK transition (0° Mode) or halfway between DCLK transitions (90° Mode). The
DDRPh Pin selects 0° Mode or 90° Mode for both the I-channel: DI- and DId-to-DCLKI phase relationship
and for the Q-channel: DQ- and DQd-to-DCLKQ phase relationship.
To use this feature in ECM, use the DPS bit in the Configuration Register (Addr: 0h; Bit: 14). See
Section 5.3.2.1 for more information.
5.5.1.1.4 Calibration Pin (CAL)
The Calibration (CAL) Pin may be used to execute an on-command calibration or to disable the power-on
calibration. The effect of calibration is to maximize the dynamic performance. To initiate an on-command
calibration via the CAL pin, bring the CAL pin high for a minimum of t_{CAL_H} input clock cycles after it has
been low for a minimum of t_{CAL_L} input clock cycles. Holding the CAL pin high upon power-on will prevent
execution of the power-on calibration. In ECM, this pin remains active and is logically OR'd with the CAL
bit.
To use this feature in ECM, use the CAL bit in the Configuration Register (Addr: 0h; Bit: 15). See
Section 5.3.3 for more information.
5.5.1.1.5 Calibration Delay Pin (CalDly)
The Calibration Delay (CalDly) Pin selects whether a shorter or longer delay time is present, after the
application of power, until the start of the power-on calibration. The actual delay time is specified as t_CalDly
and may be found in Section 4.15. This feature is pin-controlled only and remains active in ECM. It is
recommended to select the desired delay time prior to power-on and not dynamically alter this selection.
See Section 5.3.3 for more information.
5.5.1.1.6 Power Down I-channel Pin (PDI)
The Power Down I-channel (PDI) Pin selects whether the I-channel is powered down (logic-high) or active
(logic-low). The digital data output pins, DI and DId, (both positive and negative) are put into a high
impedance state when the I-channel is powered down. Upon return to the active state, the pipeline will
contain meaningless information and must be flushed. The supply currents (typicals and limits) are
available for the I-channel powered down or active and may be found in Section 4.12. The device should
be recalibrated following a power-cycle of PDI (or PDQ).
This pin remains active in ECM. In ECM, either this pin or the PDI bit (Addr: 0h; Bit: 11) in the Control
Register may be used to power-down the I-channel. See Section 5.3.4 for more information.
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