PGA900 Datasheet, PDF (61/137 Pages) Texas Instruments – PGA900 Programmable Resistive Sensing Conditioner with Digital and Analog Outputs

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PGA900
SLDS209A – JANUARY 2015 – REVISED MAY 2015
7.3.21.6 Software Development RAM
7.3.21.6.1 Software Development
PGA900 has 8 KB of development RAM that can overlay the OTP memory address. This is to allow convenient
development of software. The software development RAM can be configured to either overlay the OTP memory
address space (that is, same address space as OTP) or assigned to non-OTP-overlay address space using the
REMAP bit in the REMAP register. The REMAP can be set using a debugger.
7.3.21.6.1.1 Downloading Software into Development RAM Using Digital Interface
Follow these steps to download the software into development RAM.
1. Set REMAP bit in REMAP register to 0.
2. Select the development RAM page address by writing the appropriate page value to the
DEVRAM_PAGE_ADDR register. Note that this register is at digital interface memory page address 0x02
and each development RAM page consists of 256 bytes.
3. Write to the development RAM to the byte in the 256-byte development RAM page at digital interface
memory page address 0x03.
7.3.21.6.2 Trace FIFO
The PGA900 software development RAM can also be used as trace FIFO. The trace feature allows either P ADC
value or T ADC value to be stored in the development RAM for post-processing. The trace source can be
selected by setting the TRACE_SOURCE in the TRACE_FIFO_CTRL_STAT register. The trace function can be
enabled by writing 1 to the TRACE_FIFO_ENABLE bit in TRACE_FIFO_CTRL_STAT register.
The trace capture stops after collecting 2048 ADC samples. The samples are 32-bit address aligned with the
ADC value in the lower 16 or 24 bits depending on the configured number of ADC bits. The state of tracing can
be monitored through TRACE_FIFO_EMPTY, TRACE_FIFO_HALF_FULL, and TRACE_FIFO_FULL bits in the
TRACE_FIFO_CTRL_STAT register.
NOTE
If the trace feature is enabled, the software development RAM cannot be used to overlay
the OTP for software development.
7.3.21.7 OTP Security
7.3.21.7.1 Definition of OTP Security
OTP security is defined as the inability to read OTP memory contents with digital interfaces (SPI, I²C, and OWI)
and software debugger. This feature is implemented in PGA900 to prevent the download of OTP contents after
the device is deployed in the field.
7.3.21.7.2 OTP Security in PGA900
In PGA900, if OTP security is enabled, access to all memories is disabled. That is, after security is enabled, the
digital interface cannot access OTP, EEPROM, and RAM through digital interfaces and debugger.
However, the COMBUF register is accessible even when security is enabled.
7.3.21.7.3 Enabling OTP Security in PGA900
PGA900 will have two registers to enable OTP security
1. SECLOCK register (8 bits)
(a) Writing 0x00 enables access to all memories through digital interface.
(b) Writing 0xAA disables access to all memories through digital interface.
The reset value of the register is such that OTP security is disabled.
2. DEBUG_LOCK bit in MICRO_INTERFACE_CONTROL register
(a) Writing a 0 to this bit enables access through software debugger.
(b) Writing a 1 to this bit disables access through software debugger.
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