DAC34H84 Datasheet, PDF (61/80 Pages) Texas Instruments – Quad-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter (DAC)

DAC34H84
www.ti.com
SLAS751A – MARCH 2011 – REVISED JUNE 2011
data is only read and sent out by the digital block when the temperature sensor is read in tempdata(7:0) in
config6. The conversion uses the first eight clocks of the serial clock as the capture and conversion clock, the
data is valid on the falling eighth SCLK. The data is then clocked out of the chip on the rising edge of the ninth
SCLK. No other clocks to the chip are necessary for the temperature sensor operation. As a result the
temperature sensor is enabled even when the device is in sleep mode.
In order for the process described above to operate properly, the serial port read from config6 must be done with
an SCLK period of at least 1 μs. If this is not satisfied the temperature sensor accuracy is greatly reduced.
DATA PATTERN CHECKER
The DAC34H84 incorporates a simple pattern checker test in order to determine errors in the data interface. The
main cause of failures is setup/hold timing issues. The test mode is enabled by asserting iotest_ena in register
config1. In test mode the analog outputs are deactivated regardless of the state of TXENA or sif_texnable in
register config3.
The data pattern key used for the test is 8 words long and is specified by the contents of iotest_pattern[0:7] in
registers config37 through config44. The data pattern key can be modified by changing the contents of these
registers.
The first word in the test frame is determined by a rising edge transition in ISTR or SYNC, depending on the
syncsel_fifoin(3:0) setting in config32. At this transition, the pattern0 word should be input to the data DAB[15:0]
pins, and pattern2 should be input to the data DCD[15:0] pins. Patterns 1, 4, and 5 of DAB[15:0] bus and pattern
3, 6, and 7 of DCD[15:0] bus should follow sequentially on each edge of DATACLK (rising and falling). The
sequence should be repeated until the pattern checker test is disabled by setting iotest_ena back to “0”. It is not
necessary to have a rising ISTR or SYNC edge aligned with every four DATACLK cycle, just the first one to mark
the beginning of the series.
Start cycle again with optional rising edge of ISTR or SYNC
DAB[15:0]P/N
Pattern 0 Pattern 1 Pattern 4 Pattern 5 Pattern 0 Pattern 1 Pattern 4 Pattern 5
[15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0]
DCD[15:0]P/N
Pattern 2 Pattern 3 Pattern 6 Pattern 7 Pattern 2 Pattern 3 Pattern 6 Pattern 7
[15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0]
DATACLKP/N (DDR)
Sync
Option #1
ISTRP/N
Sync
Option #2
SYNCP/N
Figure 77. IO Pattern Checker Data Transmission Format
T0532-01
The test mode determines if the all the patterns on the two 16-bit LVDS data buses (DAB[15:0]P/N and
DCD[15:0]P/N) were received correctly by comparing the received data against the data pattern key. If any bits in
either of the two 16-bit data buses were received incorrectly, the corresponding bits in iotest_results(15:0) in
register config4 will be set to “1” to indicate bit error location. The user can check the corresponding bit location
on both 16-bit data buses and implement the fix accordingly. Furthermore, the error condition will trigger the
alarm_from_iotest bit in register config5 to indicate a general error in the data interface. When data pattern
checker mode is enabled, this alarm in register config5, bit7 is the only valid alarm. Other alarms in register
config5 are not valid and can be disregarded.
Copyright © 2011, Texas Instruments Incorporated
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