LM3S9G97_15 Datasheet, PDF (601/1341 Pages) Texas Instruments – Stellaris LM3S9G97 Microcontroller

Stellaris^® LM3S9G97 Microcontroller
Register 10: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028
This register provides a mechanism for application software to initiate sampling in the sample
sequencers. Sample sequences can be initiated individually or in any combination. When multiple
sequences are triggered simultaneously, the priority encodings in ADCSSPRI dictate execution
order.
This register also provides a means to configure and then initiate concurrent sampling on all ADC
modules. To do this, the first ADC module should be configured. The ADCPSSI register for that
module should then be written. The appropriate SS bits should be set along with the SYNCWAIT bit.
Additional ADC modules should then be configured following the same procedure. Once the final
ADC module is configured, its ADCPSSI register should be written with the appropriate SS bits set
along with the GSYNC bit. All of the ADC modules then begin concurrent sampling according to their
configuration.
ADC Processor Sample Sequence Initiate (ADCPSSI)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x028
Type R/W, reset -
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
GSYNC
reserved
SYNCWAIT
reserved
Type R/W
RO
RO
RO
R/W
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
SS3
SS2
SS1
SS0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
WO
WO
WO
WO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
Bit/Field
31
Name
GSYNC
Type
R/W
Reset
0
Description
Global Synchronize
Value Description
1 This bit initiates sampling in multiple ADC modules at the same
time. Any ADC module that has been initialized by setting an
SSn bit and the SYNCWAIT bit starts sampling once this bit is
written.
0 This bit is cleared once sampling has been initiated.
30:28
27
reserved
SYNCWAIT
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
0
Synchronize Wait
Value Description
1 This bit allows the sample sequences to be initiated, but delays
sampling until the GSYNC bit is set.
0 Sampling begins when a sample sequence has been initiated.
26:4
reserved
RO
0x0000.0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
July 03, 2014
601
Texas Instruments-Production Data