SM320C6712-EP Datasheet, PDF (60/109 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SM320C6712ĆEP, SM320C6712CĆEP, SM320C6712DĆEP
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS055 − SEPTEMBER 2004
Table 38. C6712C/C6712D Example Boards and Maximum EMIF Speed
TYPE
BOARD CONFIGURATION
EMIF INTERFACE
COMPONENTS
BOARD TRACE
SDRAM SPEED GRADE
MAXIMUM ACHIEVABLE
EMIF-SDRAM
INTERFACE SPEED
143 MHz 32-bit SDRAM (−7) 100 MHz
1-Load
One bank of one
Short Traces 32-Bit SDRAM
1 to 3-inch traces with proper
termination resistors;
Trace impedance ~ 50 Ω
166 MHz 32-bit SDRAM (−6)
183 MHz 32-bit SDRAM (−55)
200 MHz 32-bit SDRAM (−5)
For short traces, SDRAM data
output hold time on these
SDRAM speed grades cannot
meet EMIF input hold time
requirement (see NOTE 1).
2-Loads
One bank of two
Short Traces 16-Bit SDRAMs
1.2 to 3 inches from EMIF to
each load, with proper
termination resistors;
Trace impedance ~ 78 Ω
125 MHz 16-bit SDRAM (−8E)
133 MHz 16-bit SDRAM (−75)
143 MHz 16-bit SDRAM (−7E)
167 MHz 16-bit SDRAM (−6A)
167 MHz 16-bit SDRAM (−6)
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
3-Loads
Short Traces
One bank of two
32-Bit SDRAMs
One bank of buffer
1.2 to 3 inches from EMIF to
each load, with proper
termination resistors;
Trace impedance ~ 78 Ω
125 MHz 16-bit SDRAM (−8E)
133 MHz 16-bit SDRAM (−75)
143 MHz 16-bit SDRAM (−7E)
167 MHz 16-bit SDRAM (−6A)
167 MHz 16-bit SDRAM (−6)
For short traces, EMIF cannot
meet SDRAM input hold
requirement (see NOTE 1).
100 MHz
100 MHz
100 MHz
For short traces, EMIF cannot
meet SDRAM input hold
requirement (see NOTE 1).
3-Loads
Long Traces
One bank of one
32-Bit SDRAM
One bank of one
32-Bit SBSRAM
One bank of buffer
4 to 7 inches from EMIF;
Trace impedance ~ 63 Ω
143 MHz 32-bit SDRAM (−7)
166 MHz 32-bit SDRAM (−6)
183 MHz 32-bit SDRAM (−55)
200 MHz 32-bit SDRAM (−5)
83 MHz
83 MHz
83 MHz
SDRAM data output hold time
cannot meet EMIF input hold
requirement (see NOTE 1).
NOTE 1: Results are based on IBIS simulations for the given example boards (TYPE). Timing analysis should be performed to determine if timing
requirements can be met for the particular system.
EMIF big endian mode correctness [C6712D only]
The device Endian mode pin (LENDIAN) selects the endian mode of operation (little endian or big endian) for
the C6712D device. Little endian is the default setting.
When Big Endian mode is selected (LENDIAN = 0), the EMIF Big Endian mode correctness pin (EMIFBE) must
to be pulled low. Figure 16 shows the mapping of 16-bit and 8-bit data for C6712D devices with EMIF
endianness correction.
EMIF DATA LINES (PINS) WHERE DATA PRESENT
ED[15:8] (BE1)
ED[7:0] (BE0)
16-Bit Device in Any Endianness Mode
† _{The C6712/C6712C devices support Little Endian mode of operation only.}
8-Bit Device in Any Endianness Mode
Figure 16. 16/8-Bit EMIF Big Endian Mode Correctness Mapping [C6712D Only]^†
This new feature does not affect systems operating in Little Endian mode, providing the default value of the C15
pin =1 is used.
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