TSC2100_16 Datasheet, PDF (6/77 Pages) Texas Instruments – PROGRAMMABLE TOUCH SCREEN CONTROLLER WITH INTEGRATED

TSC2100
SLAS378− NOVEMBER 2003
www.ti.com
ELECTRICAL CHARACTERISTICS
At +25°C, AVDD,DRVDD,IOVDD = 3.3 V, DVDD = 1.8 V, Int. V_ref = 2.5 V, Fs (Audio) = 48 kHz, unless otherwise noted (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VOLTAGE REFERENCE
Voltage range
VREF output programmed as 2.5 V
VREF output programmed as 1.25 V
2.3
2.5
1.15 1.25
2.7
V
1.35
Voltage range
External VREF. By design, not tested in
1.2
production.
2.55 V
Reference drift
Internal VREF = 1.25 V
29
ppm/°C
Current drain
Extra current drawn when the internal
reference is turned on.
650
µA
DIGITAL INPUT / OUTPUT⁽¹⁾
Internal clock frequency
8.8
MHz
Logic family
CMOS
Logic level: V_IH
V_IL
V_OH
V_OL
Capacitive load
I_IH = +5 µA
I_IL = +5 µA
I_OH = 2 TTL loads
I_OL = 2 TTL loads
0.7xIOVDD
−0.3
0.8xIOVDD
V
0.3xIOVDD V
V
0.1xIOVDD V
10
pF
POWER SUPPLY REQUIREMENTS
Power supply voltage
AVDD⁽²⁾
DRVDD⁽²⁾
2.7
3.6 V
2.7
3.6
V
IOVDD
1.1
3.6 V
DVDD
1.525
1.95 V
Touch-screen ADC quiescent current
IAVDD
IDRVDD
IDVDD
Host controlled AUX
conversion at
10 ksps with external
reference.
47
0
µA
65
Stereo audio playback
IAVDD
IDRVDD
IDVDD
48 ksps, output drivers in low
power mode, VGND off, PLL
off
2.2
0
mA
2.4
IAVDD
2.9
Microphone record
IDRVDD 48 ksps, no playback, PLL off
0
mA
IDVDD
1.4
IAVDD
0.1
PLL
IDRVDD
Additional power consumed
when PLL is enabled.
1.3
mA
IDVDD
0.9
VGND
IAVDD
IDRVDD
IDVDD
Additional power consumed
when VGND is powered.
0.3
0.9
mA
0
Hardware power down
All currents
2
µA
(1) _{Internal oscillator is designed to give nominally 8-MHz clock frequency. However, due to process variations, this frequency can vary from device}
to device. All calculations for delays and wait times in the data sheet assume an 8-MHz oscillator clock.
(2) _{It is recommended that AVDD and DRVDD be set to the same voltage for the best performance. It is also recommended that these supplies be}
separated on the user’s PCB.
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