TPS3808_16 Datasheet, PDF (6/32 Pages) Texas Instruments – Low-Quiescent-Current, Programmable-Delay Supervisory Circuit

TPS3808
SBVS050K – MAY 2004 – REVISED OCTOBER 2015
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7.5 Electrical Characteristics
1.7 V ≤ V_DD ≤ 6.5 V, R_LRESET = 100 kΩ, C_LRESET = 50 pF, over operating temperature range (T_J = –40°C to 125°C), unless
otherwise noted. Typical values are at T_J = 25°C⁽¹⁾.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
V_DD
Input supply range
I_DD
Supply current (current into V_DD pin)
V_OL
V_POR
Low-level output voltage
Power-up reset voltage⁽²⁾
TPS3808G01
–40°C < T_J < 125°C
0°C < T_J < 85°C
V_DD = 3.3 V, RESET not asserted
MR, RESET, C_T open
V_DD = 6.5 V, RESET not asserted
MR, RESET, C_T open
1.3 V ≤ V_DD < 1.8 V, I_OL = 0.4 mA
1.8 V ≤ V_DD ≤ 6.5 V, I_OL = 1 mA
V_OL (max) = 0.2 V, I_RESET = 15 μA
1.7
1.65
2.4
2.7
–2% ±1%
6.5 V
6.5 V
5
μA
6
0.3
0.4 V
0.8
2%
V_IT
V_HYS
Negative-going input
threshold accuracy
Hysteresis on V_IT pin
V_IT ≤ 3.3 V
3.3 V < V_IT ≤ 5.0 V
V_IT ≤ 3.3 V
3.3 V < V_IT ≤ 5.0 V
TPS3808G01
Fixed versions
–40°C < T_J < 85°C
–40°C < T_J < 85°C
–1.5% ±0.5% 1.5%
–2% ±1%
2%
–1.25% ±0.5% 1.25%
–1.5% ±0.5% 1.5%
1.5%
1%
3%
2.5% ^VIT
R_MR
I_SENSE
I_OH
C_IN
V_IL
V_IH
MR Internal pullup resistance
Input current at
SENSE pin
TPS3808G01
Fixed versions
RESET leakage current
Input capacitance,
any pin
C_T pin
Other pins
MR logic low input
MR logic high input
V_SENSE = V_IT
V_SENSE = 6.5 V
V_RESET = 6.5 V, RESET not asserted
V_IN = 0 V to V_DD
V_IN = 0 V to 6.5 V
70
–25
0
0.7 V_DD
90
kΩ
25 nA
1.7
μA
300 nA
5
pF
5
0.3 V_DD
V
V_DD
(1) R_LRESET and C_LRESET are the resistor and capacitor connected to the RESET pin.
(2) The lowest supply voltage (V_DD) at which RESET becomes active. T_rise(VDD) ≥ 15 μs/V.
6
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