TPS3808_16 Datasheet, PDF (4/32 Pages) Texas Instruments – Low-Quiescent-Current, Programmable-Delay Supervisory Circuit

TPS3808
SBVS050K – MAY 2004 – REVISED OCTOBER 2015
6 Pin Configuration and Functions
DBV Package
6-Pin SOT-23
Top View
RESET
1
GND
2
MR
3
6
V_DD
5
SENSE
4
C_T
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DRV Package
6-Pin (2.00 mm × 2.00 mm) WSON With Thermal Pad
Top View
V_{DD 1}
6
THERMAL
SENSE 2
PAD
5
C_{T 3}
4
RESET
GND
MR
NAME
C_T
GND
MR
RESET
SENSE
V_DD
Thermal
Pad
PIN
SOT-23
WSON
4
3
2
5
3
4
1
6
5
2
6
1
—
Pad
Pin Functions
I/O
DESCRIPTION
Reset period programming pin. Connecting this pin to V_DD through a 40-kΩ to 200-kΩ
I
resistor or leaving it open results in fixed delay times (see Electrical Characteristics).
Connecting this pin to a ground referenced capacitor ≥ 100 pF gives a user-programmable
delay time. See the Selecting the RESET Delay Time section for more information.
— Ground
I
Driving the manual reset pin (MR) low asserts RESET. MR is internally tied to V_DD by a 90-
kΩ pull-up resistor.
RESET is an open-drain output that is driven to a low-impedance state when RESET is
asserted (either the SENSE input is lower than the threshold voltage (V_IT) or the MR pin is
O set to a logic low). RESET remains low (asserted) for the reset period after both SENSE is
above V_IT and MR is set to a logic high. A pull-up resistor from 10 kΩ to 1 MΩ should be
used on this pin, and allows the reset pin to attain voltages higher than V_DD.
I
This pin is connected to the voltage to be monitored. If the voltage at this terminal drops
below the threshold voltage V_IT, then RESET is asserted.
I
Supply voltage. It is good analog design practice to place a 0.1-μF ceramic capacitor close
to this pin.
— Thermal Pad. Connect to ground plane to enhance thermal performance of package.
4
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