TLC7628C_16 Datasheet, PDF (6/18 Pages) Texas Instruments – DUAL 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTER

TLC7628C
DUAL 8ĆBIT MULTIPLYING
SLAS063B − APRIL 1989 − REVISED MARCH 2007
APPLICATION INFORMATION
VI(A)
±10 V
R6 (see Note B)
R1 (see Note A)
20 kΩ
R2 (see Note A)
VDD
17
14
DBO
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{7 DB7}
Input
Buffer
REFA
RFBA
8
8
OUTA
Latch
DACA
C1(see Note C)
(see
Note B)
AGND ^A1
R7
10 kΩ
R11
R5
20 kΩ
A2
VOA
DACA/
6 DACB
ÎÎÎÎÎ _{15 CS}
ÎÎÎÎÎ ÎÎÎÎÎÎÎ _{16 WR}
Control
Logic
ÎÎÎÎÎ ÎÎÎÎÎÎÎ ₅
ÎÎÎÎÎÎÎ _DGND
RFBA
8
Latch
8
OUTB
DACB
REFB
R4 (see Note A)
C2
(see Note C)
A3
5 kΩ
(see
Note B)
R9
10 kΩ
R8
20 kΩ
A4
VOB
RECOMMENDED TRIM
RESISTOR VALUES
R1, R3 500 Ω
R2, R4 150 Ω
R3 (see Note A) ^AGND
±10 V
VI(B)
(see Note B)
R10
20 kΩ
R12
5 kΩ
NOTES: A. R1, R2, R3, and R4 are used only if gain adjustment is required. See table for recommended values. Adjust R1 for VOA = 0 V with
code 10000000 in DACA latch. Adjust R3 for VOB = 0 V with 10000000 in DACB latch.
B. Matching and tracking are essential for resistor pairs R6, R7, R9, and R10.
C. C1 and C2 phase compensation capacitors (10 pF to 15 pF) may be required if A1 and A3 are high-speed amplifiers.
Figure 3. Bipolar Operation (4-Quadrant Operation)
A8−A15
CPU
8051
WR
ALE
Address Bus
Address
Decode
Logic
A
A+1
Latch
DACA/DACB
CS
TLC7628
WR
DB0
DB7
AD0−AD7
Data Bus
NOTE D: A = decoded address for TLC7628 DACA
A + 1 = decoded address for TLC7628 DACB
Figure 4. TLC7628 — Intel 8051 Interface
6
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