TLC7628C_16 Datasheet, PDF (4/18 Pages) Texas Instruments – DUAL 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTER

TLC7628C
DUAL 8ĆBIT MULTIPLYING
SLAS063B − APRIL 1989 − REVISED MARCH 2007
operating characteristics over recommended ranges of operating free-air temperature and V_DD,
V_refA = V_refB = 10 V, V_OA and V_OB at 0 V (unless otherwise noted)
PARAMETER
Linearity error
Settling time (to 1/2 LSB)
Gain error
AC feedthrough
REFA to OUTA
REFB to OUTB
Temperature coefficient of gain
See Note 1
See Note 2
See Note 3
TEST CONDITIONS
Full range
25°C
Full range
25°C
MIN TYP MAX
UNIT
± 1/2
LSB
100
ns
±3
LSB
±2
− 65
dB
− 75
± 0.0035 %FSR/°C
Propagation delay (from digital input to
90% of final analog output current)
See Note 4
80
ns
Channel-to-channel ^{REFA to OUTB}
isolation
REFB to OUTA
See Note 5
See Note 6
25°C
25°C
80
dB
80
Digital-to-analog glitch impulse area
Measured for code transition from 00000000 to 11111111,
TA = 25°C
330
nV•s
Digital crosstalk
Measured for code transition from 00000000 to 11111111,
TA = 25°C
60
nV•s
Harmonic distortion
Vi = 6 V, f = 1 kHz, TA = 25°C
− 85
dB
NOTES:
1. OUTA, OUTB load = 100 Ω, Cext = 13 pF; WR and CS at 0 V; DB0−DB7 at 0 V to VDD or VDD to 0 V.
2. Gain error is measured using an internal feedback resistor. Nominal full scale range (FSR) = Vref − 1 LSB. Both DAC latches are
loaded with 11111111.
3. Vref = 20 V peak-to-peak, 10-kHz sine wave
4. VrefA = VrefB = 10 V; OUTA/OUTB load = 100 Ω, Cext = 13 pF; WR and CS at 0 V; DB0−DB7 at 0 V to VDD or VDD to 0 V.
5. VrefA = 20 V peak-to-peak, 10-kHz sine wave; VrefB = 0
6. VrefB = 20 V peak-to-peak, 10-kHz sine wave; VrefA = 0
CS
DACA/DACB
WR
DB0 −DB7
ÏÏÏ ^tsu(CS)
th(CS)
1.3 V
3.5 V
1.3 V
ÏÏÏÏ ^tsu(DAC)
0.3 V
th(DAC)
3.5 V
1.3 V
ÏÏÏÏÏÏ _tw(WR)
1.3 V
0.3 V
3.5 V
1.3 V
ÏÏÏÏÏÏ ^{1.3 V}
tsu(D)
th(D)
0.3 V
3.5 V
1.3 V
Data In Stable
1.3 V
0.3 V
For all input signals, tr = tf = 5 ns (10% to 90% points).
Figure 1. Setup and Hold Times
4
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