THS5641AIDWG4 Datasheet, PDF (6/31 Pages) Texas Instruments – 8-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER

THS5641A
8ĆBIT, 100 MSPS, CommsDAC
DIGITALĆTOĆANALOG CONVERTER
SLAS277A −MARCH 2000 − REVISED SEPTEMBER 2002
electrical characteristics over recommended operating free-air temperature range, AV_DD = 5 V,
DV_DD = 5 V, IOUT_FS = 20 mA, single-ended output IOUT1, 50 Ω doubly terminated load (unless
otherwise noted) (continued)
ac specifications
PARAMETER
AC linearity (to Nyquist)
SFDR Spurious free dynamic range
TEST CONDITIONS
fCLK = 5 MSPS, fOUT = 1 MHz, TA = 25°C
fCLK = 25 MSPS, fOUT = 1 MHz, TA = 25°C
fCLK = 25 MSPS, fOUT = 5 MHz, TA = 25°C
fCLK = 25 MSPS, fOUT = 10 MHz, TA = 25°C
fCLK = 50 MSPS, fOUT = 1 MHz, TA = 25°C
fCLK = 50 MSPS, fOUT = 5 MHz, TA = 25°C
fCLK = 50 MSPS, fOUT = 20 MHz, TA = 25°C
fCLK = 70 MSPS, fOUT = 5 MHz, TA = 25°C
fCLK = 70 MSPS, fOUT = 10 MHz, TA = 25°C
fCLK = 70 MSPS, fOUT = 20 MHz, TA = 25°C
fCLK = 100 MSPS, fOUT = 10 MHz, TA = 25°C
fCLK = 100 MSPS, fOUT = 22 MHz, TA = 25°C
fCLK = 100 MSPS, fOUT = 40 MHz, TA = 25°C
MIN TYP MAX UNIT
68
69
68
56
67
67
53
dBc
65
63
48
55
55
48
digital specifications
Interface
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
IIH
High-level input current
IIL
Low-level input current
CI
Timing
Input capacitance
tsu(D)
th(D)
tw(LPH)
td(D)
Input setup time
Input hold time
Input latch pulse high time
Digital delay time
Specifications subject to change
MODE and SLEEP
All other digital pins
MODE and SLEEP
All other digital pins
TEST CONDITIONS
DVDD = 5 V
DVDD = 3.3 V
DVDD = 5 V
DVDD = 3.3 V
DVDD = 3 V to 5.5 V
DVDD = 3 V to 5.5 V
DVDD = 3 V to 5.5 V
DVDD = 3 V to 5.5 V
MIN TYP MAX UNIT
3.5
5
V
2.1 3.3
0 1.3
V
0 0.9
−15
15
µA
−10
10
−15
15
µA
−10
10
1
5 pF
1
ns
1
ns
4
ns
1 clk
6
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