SN74LV74A-Q1_15 Datasheet, PDF (6/15 Pages) Texas Instruments – DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

SN74LV74A-Q1
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SCLS556B − DECEMBER 2003 − REVISED APRIL 2008
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
C_L
(see Note A)
Test
Point
From Output
Under Test
C_L
(see Note A)
R_L = 1 kΩ ^S1
V_CC
Open
GND
TEST
t_PLH/t_PHL
t_PLZ/t_PZL
t_PHZ/t_PZH
Open Drain
S1
Open
V_CC
GND
V_CC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
Input
t_w
50% V_CC
V_CC
50% V_CC
0V
VOLTAGE WAVEFORMS
PULSE DURATION
Timing Input
V_CC
50% V_CC
0V
t_h
t_su
V_CC
Data Input
50% V_CC
50% V_CC
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Input
50% V_CC
V_CC
50% V_CC
0V
Output
Control
50% V_CC
V_CC
50% V_CC
0V
t_PLH
In-Phase
Output
50% V_CC
t_PHL
V_OH
50% V_CC
V_OL
t_PHL
t_PLH
Out-of-Phase
Output
50% V_CC
V_OH
50% V_CC
V_OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 1
S1 at V_CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t_PZL
50% V_CC
t_PLZ
≈V_CC
V_OL + 0.3 V _VOL
t_PZH
50% V_CC
t_PHZ
V_OH − 0.3 V ^VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C_L includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z_O = 50 Ω, t_r ≤ 3 ns, t_f ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. t_PLZ and t_PHZ are the same as t_dis.
F. t_PZL and t_PZH are the same as t_en.
G. t_PHL and t_PLH are the same as t_pd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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